AM486DX2 datasheet(7/67 Pages) AMD

7 / 67 page

AMD

PRELIMINARY

Am5X86 Microprocessor

Figure 30 SMM Base Slot Offset ............................................................................................................. 48

Figure 31 SRAM Usage .......................................................................................................................... 48

Figure 32 SMRAM Location .................................................................................................................... 49

Figure 33 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode

with Caching Enabled During SMM.......................................................................................... 50

Figure 34 SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with

Caching Enabled During SMM ................................................................................................. 50

Figure 35 SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with

Caching Disabled During SMM ................................................................................................ 50

Figure 36 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with

Caching Enabled During SMM ................................................................................................. 51

Figure 37 SMM Timing in Systems Using Overlaid Memory Spaces and Write-Through Mode with

Caching Disabled During SMM ................................................................................................ 51

Figure 38 SMM Timing in Systems Using Overlaid Memory Spaces and Configured in

Write-Back Mode...................................................................................................................... 51

Figure 39 CLK Waveforms ...................................................................................................................... 61

Figure 40 Output Valid Delay Timing ...................................................................................................... 61

Figure 41 Maximum Float Delay Timing .................................................................................................. 62

Figure 42 PCHK Valid Delay Timing ....................................................................................................... 62

Figure 43 Input Setup and Hold Timing ................................................................................................... 63

Figure 44 RDY and BRDY Input Setup and Hold Timing ........................................................................ 63

Figure 45 TCK Waveforms ...................................................................................................................... 64

Figure 46 Test Signal Timing Diagram .................................................................................................... 64

LIST OF TABLES

Table 1

Clocking Options ....................................................................................................................... 1

Table 2

EADS Sample Time ................................................................................................................ 14

Table 3

Cache Line Organization ......................................................................................................... 19

Table 4

Legal Cache Line States ......................................................................................................... 19

Table 5

MESI Cache Line Status ......................................................................................................... 20

Table 6

Key to Switching Waveforms ................................................................................................... 22

Table 7

WBINVD/INVD Special Bus Cycles ......................................................................................... 33

Table 8

FLUSH Special Bus Cycles ..................................................................................................... 34

Table 9

Pin State during Stop Grant Bus State .................................................................................... 37

Table 10

SMRAM State Save Map ........................................................................................................ 43

Table 11

SMM Initial CPU Core Register Settings ................................................................................. 45

Table 12

Segment Register Initial States ............................................................................................... 45

Table 13

SMM Revision Identifier .......................................................................................................... 46

Table 14

SMM Revision Identifier Bit Definitions ................................................................................... 46

Table 15

HALT Auto Restart Configuration ............................................................................................ 47

Table 16

I/O Trap Word Configuration ................................................................................................... 47

Table 17

Test Register TR4 Bit Descriptions ......................................................................................... 53

Table 18

Test Register TR5 Bit Descriptions ......................................................................................... 53

Table 19

CPU ID Codes ......................................................................................................................... 56

Table 20

CPUID Instruction Description ................................................................................................. 56

Table 21

Thermal Resistance (°C/W)

JC and θJA for the Am5

X86 CPU in 168-Pin PGA Package ....... 65

Table 22

Maximum T

A at Various Airflows in °C .................................................................................... 65

Table 23

Maximum T

A for SQFP Package by Clock Frequency ............................................................. 65

AM486DX2 数据表(PDF) 7 Page - Advanced Micro Devices

AM486DX2 数据表(HTML) 7 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载