AM486DX2 datasheet(36/67 Pages) AMD

36 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

4.10.3 PLOCK Operation in Write-Through Mode

As described in Section 3, PLOCK is only used in Write-

through mode; the signal is driven inactive in Write-back

mode. In Write-through mode, the processor drives

PLOCK Low to indicate that the current bus transaction

requires more than one bus cycle. The CPU continues

to drive the signal Low until the transaction is completed,

whether or not RDY or BRDY is returned. Refer to the

pin description for additional information.

CLOCK CONTROL

5.1

Clock Generation

The Am5X86 CPU is driven by a 1x clock that relies on

phased-lock loop (PLL) to generate the two internal

clock phases: phase one and phase two. The rising edge

of CLK corresponds to the start of phase one (ph1). All

external timing parameters are specified relative to the

rising edge of CLK.

5.2

Stop Clock

The Am5X86 CPU also provides an interrupt mecha-

nism, STPCLK, that allows system hardware to control

the power consumption of the CPU by stopping the in-

ternal clock to the CPU core in a sequenced manner.

The first low-power state is called the Stop Grant state.

If the CLK input is completely stopped, the CPU enters

into the Stop Clock state (the lowest power state). When

the CPU recognizes a STPCLK interrupt, the processor:

s Stops execution on the next instruction boundary

(unless superseded by a higher priority interrupt)

s Waits for completion of cache flush

s Stops the pre-fetch unit

s Empties all internal pipelines and write buffers

s Generates a Stop Grant bus cycle

s Stops the internal clock

At this point the CPU is in the Stop Grant state.

The CPU cannot respond to a STPCLK request from an

HLDA state because it cannot empty the write buffers

and, therefore, cannot generate a Stop Grant cycle. The

rising edge of STPCLK signals the CPU to return to

program execution at the instruction following the inter-

rupted instruction. Unlike the normal interrupts (INTR

and NMI), STPCLK does not initiate interrupt acknowl-

edge cycles or interrupt table reads.

5.2.1

External Interrupts in Order of Priority

In Write-through mode, the priority order of external in-

terrupts is:

1. RESET/SRESET

2. FLUSH

3. SMI

4. NMI

5. INTR

6. STPCLK

In Write-back mode, the priority order of external inter-

rupts is:

1. RESET

2. FLUSH

3. SRESET

4. SMI

5. NMI

6. INTR

7. STPCLK

STPCLK is active Low and has an internal pull-up re-

sistor. STPCLK is asynchronous, but setup and hold

times must be met to ensure recognition in any specific

clock. STPCLK must remain active until the Stop Grant

special bus cycle is asserted and the system responds

with either RDY or BRDY. When the CPU enters the

Stop Grant state, the internal pull-up resistor is disabled,

reducing the CPU power consumption. The STPCLK

input must be driven High (not floated) to exit the Stop

Grant state. STPCLK must be deasserted for a minimum

of five clocks after RDY or BRDY is returned active for

the Stop Grant bus cycle before being asserted again.

There are two regions for the Low-power mode supply

current:

Low Power: Stop Grant state (fast wake-up, frequency-

and voltage-dependent)

Lowest Power: Stop Clock state (slow wake-up, volt-

age-dependent)

5.3

Stop Grant Bus Cycle

The processor drives a special Stop Grant bus cycle to

the bus after recognizing the STPCLK interrupt. This

bus cycle is the same as the HALT cycle used by a

standard Am486 microprocessor, with the exception

that the Stop Grant bus cycle drives the value 0000

0010h on the address pins.

s M/lO = 0

s D/C = 0

s W/R =1

s Address Bus = 0000 0010h (A

4 = 1)

s BE3–BE0 = 1011

s Data bus = undefined

The system hardware must acknowledge this cycle by

returning RDY or BRDY, or the processor will not enter

the Stop Grant state (see Figure 19). The latency be-

tween a STPCLK request and the Stop Grant bus cycle

depends on the current instruction, the amount of data

in the CPU write buffers, and the system memory per-

formance.

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