AM486DX2 datasheet(33/67 Pages) AMD

33 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

4.9

Cache Invalidation and Flushing in

Write-Back Mode

The Am5X86 microprocessor family supports cache in-

validation and flushing, much like the Am486 micropro-

cessor Write-through mode. However, the addition of

the write-back cache adds some complexity.

4.9.1

Cache Invalidation through Software

To invalidate the on-chip cache, the Am5X86 micropro-

cessor family uses the same instructions as the Am486

microprocessor family. The two invalidation instruc-

tions, INVD and WBINVD, while similar, are slightly dif-

ferent for use in the write-back environment.

The WBINVD instruction first performs a write-back of

the modified data in the cache to external memory. Then

it invalidates the cache, followed by two special bus

cycles. The INVD instruction only invalidates the cache,

regardless of whether modified data exists, and follows

with a special bus cycle. The utmost care should be

taken when executing the INVD instruction to ensure

memory coherency. Otherwise, modified data may be

invalidated prior to writing back to main memory. In

Write-back mode, WBINVD requires a minimum of 4100

internal clocks to search the cache for modified data.

Writing back modified data adds to this minimum time.

WBINVD can only be stopped by a RESET.

Two special bus cycles follow the write-back of modified

data upon execution of the WBINVD instruction: first the

write-back, and then the flush special bus cycle. The

INVD operates identically to the standard 486 micropro-

cessor family in that the flush special bus cycle is gen-

erated when the on-chip cache is invalidated. Table 7

specifies the special bus cycle states for the instructions

WBINVD and INVD.

4.9.2

Cache Invalidation through Hardware

The other mechanism for cache invalidation is the

FLUSH pin. The FLUSH pin operates similarly to the

WBINVD command, writing back modified cache lines

to main memory. After the entire cache has copied back

all the modified data, the microprocessor generates two

special bus cycles. These special bus cycles signal to

the external caches that the microprocessor on-chip

cache has completed its copy-back and that the second

level cache may begin its copy-back to memory, if so

required.

Two flush acknowledge cycles are generated after the

FLUSH pin is asserted and the modified data in the

cache is written back. As with the WBINVD instruction,

in Write-back mode, a flush requires a minimum of 4100

internal clocks to test the cache for modified data. Writ-

ing back modified data adds to this minimum time. The

flush operation can only be stopped by a RESET. Table

8 shows the special flush bus cycle configuration.

Table 7. WBINVD/INVD Special Bus Cycles

A32–A2

M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle

0000 0000 h

Write-back1

0000 0000 h

Flush1, 2

Notes:

1. WBINVD generates first write-back, then flush.

2. INVD generates only flush.

BRDY

BLAST

ADS

HITM

EADS

AHOLD

ADR

CLK

Figure 15. Latest Snooping of Copy-Back

CACHE

Address B

AM486DX2 数据表(PDF) 33 Page - Advanced Micro Devices

AM486DX2 数据表(HTML) 33 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载