AM486DX2 datasheet(54/67 Pages) AMD

54 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

s STn (bits 30–29): Read Only, available only in Write-

back mode when Ext=1 in TR5. STn returns the sta-

tus of the set (ST3, ST2, ST1, or ST0) specified by

the TR5 Set State field (bits 18–17) during cache

look-ups. Returned values are:

—00 = invalid

— 01 = exclusive

— 10 = modified

— 11 = shared

s ST3 (bits 27–26): Read Only, available only in Write-

back mode when Ext=1 in TR5. ST3 returns the sta-

tus of Set 3 during cache look-ups. Returned values

are:

—00 = invalid

— 01 = exclusive

— 10 = modified

— 11 = shared

s ST2 (bits 25–24): Read Only, available only in Write-

back mode when Ext=1 in TR5. ST2 returns the sta-

tus of Set 2 during cache look-ups. Returned values

are:

—00 = invalid

— 01 = exclusive

— 10 = modified

— 11 = shared

s ST1 (bits 23–22): Read Only, available only in Write-

back mode when Ext=1 in TR5. ST1 returns the sta-

tus of Set 1 during cache look-ups. Returned values

are:

—00 = invalid

— 01 = exclusive

— 10 = modified

— 11 = shared

s ST0 (bits 21–20): Read Only, available only in Write-

back mode when Ext=1 in TR5. ST0 returns the sta-

tus of Set 0 during cache look-ups. Returned values

are:

—00 = invalid

— 01 = exclusive

— 10 = modified

— 11 = shared

s Valid (bit 10): Read/Write, independent of the Ext bit

in TR5. This is the Valid bit for the accessed entry.

On a cache look-up, Valid is a copy of one of the bits

reported in bits 6–3. On a cache write in Write-

through mode, Valid becomes the new Valid bit for

the selected entry and set. In Write-back mode, writ-

ing to the Valid bit has no effect and is ignored; the

Set State bit locations in TR5 are used to set the

Valid bit for the selected entry and set.

s LRU (bits 9–7): Read Only, independent of the Ext

bit in TR5. On a cache look-up, these are the three

LRU bits of the accessed set. On a cache write,

these bits are ignored; the LRU bits in the cache are

updated by the pseudo-LRU cache replacement al-

gorithm. Write operations to these locations have

no effect on the device.

s Valid (bits 6–3): Read Only, independent of the Ext

bit in TR5. On a cache look-up, these are the four

Valid bits of the accessed set. In Write-back mode,

these valid bits are set if a cache set is in the exclu-

sive, modified, or shared state. Write operations to

these locations have no effect on the device.

8.2

TR5 Definition

This section includes a detailed description of the bit

fields in the TR5.

Note: Bits listed in Table 18 as Reserved or Not Used

are not included in the descriptions.

s Ext (bit 19): Read/Write, available only in Write-back

mode. Ext, or extension, determines which bit fields

are defined for TR4: the address TAG field, or the

STn and ST3–ST0 status bit fields. In Write-through

mode, the Ext bit is not accessible. The following

describes the two states of Ext:

— Ext = 0, bits 31–11 of TR4 contain the TAG ad-

dress

— Ext = 1, bits 30–29 of TR4 contain STn, bits 27–

20 contain ST3–ST0

s Set State (bits 18–17): Read/Write, available only in

Write-back mode. The Set State field is used to

change the MESI state of the set specified by the

Index and Entry bits. The state is set by writing one

of the following combinations to this field:

— 00 = invalid

— 01 = exclusive

— 10 = modified

— 11 = shared

s Index (bits 11–4): Read/Write, independent of write-

through or Write-back mode. Index selects one of

the 256 cache lines.

s Entry (bits 3–2): Read/Write, independent of write-

through or Write-back mode. Entry selects between

one of the four entries in the set addressed by the

Set Select during a cache read or write. During

cache fill buffer writes or cache read buffer reads,

the value in the Entry field selects one of the four

doublewords in a cache line.

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