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AM486DX2 数据表(PDF) 50 Page - Advanced Micro Devices |
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AM486DX2 数据表(HTML) 50 Page - Advanced Micro Devices |
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50 / 67 page ![]() 50 Am5X86 Microprocessor AMD PRELIMINARY State Save SMI Handler State Resume Normal Cycle RSM SMI SMIACT Figure 33. SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode with Caching Enabled During SMM Figure 34. SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with Caching Enabled During SMM State Save SMI Handler State Resume Normal Cycle RSM SMI SMIACT Note: For proper operation of systems configured in Write-back mode when caching during SMM is allowed, force WB/WT Low to force all caching to be write-through during SMM. WB/WT Figure 35. SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with Caching Disabled During SMM State Save SMI Handler State Resume Normal Cycle RSM SMI SMIACT KEN |
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