AM486DX2 datasheet(38/67 Pages) AMD

38 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

Figure 20. Stop Clock State Machine

(valid for Write-back mode only)

Figure 21. Recognition of Inputs when Exiting Stop Grant State

t20

t21

CLK

STPCLK

NMI

SMI

STPCLK

Sampled

Note: A = Earliest time at which NMI or SMI is recognized.

A RESET or SRESET brings the CPU from the Stop

Grant state to the Normal state. The CPU recognizes

the inputs required for cache invalidations (HOLD,

AHOLD, BOFF, and EADS) as explained later. The CPU

does not recognize any other inputs while in the Stop

Grant state. Input signals to the CPU are not recognized

until 1 clock after STPCLK is deasserted (see Figure 21).

While in the Stop Grant state, the CPU does not recog-

nize transitions on the interrupt signals (SMI, NMI, and

INTR). Driving an active edge on either SMI or NMI does

not guarantee recognition and service of the interrupt

request following exit from the Stop Grant state. How-

ever, if one of the interrupt signals (SMI, NMI, or INTR)

is driven active while the CPU is in the Stop Grant state,

and held active for at least one CLK after STPCLK is

deasserted, the corresponding interrupt will be serviced.

AM486DX2 数据表(PDF) 38 Page - Advanced Micro Devices