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AM486DX2 数据表(PDF) 59 Page - Advanced Micro Devices |
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AM486DX2 数据表(HTML) 59 Page - Advanced Micro Devices |
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59 / 67 page  Am5X86 Microprocessor 59 AMD PRELIMINARY The AC specifications, provided in the AC characteris- tics table, consist of output delays, input setup require- ments, and input hold requirements. All AC specifica- tions are relative to the rising edge of the CLK signal. AC specifications measurement is defined by Figure 39. All timings are referenced to 1.5 V unless otherwise specified. Am5X86 microprocessor output delays are specified with minimum and maximum limits, measured as shown. The minimum microprocessor delay times are hold times provided to external circuitry. Input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. Within the sam- pling window, a synchronous input signal must be stable for correct microprocessor operation. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges 33-MHz bus (133-MHz operating frequency) V CC = 3.3 V ±0.3 V; TCASE = 0°C to + 85°C; CL = 50 pF unless otherwise specified Preliminary Info Symbol Parameter Min Max Unit Figure Notes Frequency 8 33 MHz Note 2 t1 CLK Period 30 125 ns 39 t1a CLK Period Stability 0.1% ∆ Adjacent Clocks Notes 3 and 4 t2 CLK High Time at 2 V 11 ns 39 Note 3 t3 CLK Low Time at 0.8 V 11 ns 39 Note 3 t4 CLK Fall Time (2 V–0.8 V) 3 ns 39 Note 3 t5 CLK Rise Time (0.8 V–2 V) 3 ns 39 Note 3 t6 A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE, W/R, ADS, LOCK, FERR, BREQ, HLDA, SMIACT, HITM Valid Delay 3 14 ns 40 Note 5 t7 A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE, W/R, ADS, LOCK Float Delay 3 20 ns 41 Note 3 t8 PCHK Valid Delay 3 14 ns 42 t8a BLAST, PLOCK, Valid Delay 3 14 ns 40 t9 BLAST, PLOCK, Float Delay 3 20 ns 41 Note 3 t10 D31–D0, DP3–DP0 Write Data Valid Delay 3 14 ns 40 t11 D31–D0, DP3–DP0 Write Data Float Delay 3 20 ns 41 Note 3 t12 EADS, INV, WB/WT Setup Time 5 ns 43 t13 EADS, INV, WB/WT Hold Time 3 ns 43 t14 KEN, BS16, BS8 Setup Time 5 ns 43 t15 KEN, BS16, BS8 Hold Time 3 ns 43 t16 RDY, BRDY Setup Time 5 ns 44 t17 RDY, BRDY Hold Time 3 ns 44 t18 HOLD, AHOLD Setup Time 6 ns 43 t18a BOFF Setup Time 7 ns 43 t19 HOLD, AHOLD, BOFF Hold Time 3 ns 43 t20 RESET, FLUSH, A20M, NMI, INTR, IGNNE, STPCLK, SRESET, SMI Setup Time 5 ns 43 Note 5 t21 RESET, FLUSH, A20M, NMI, INTR, IGNNE, STPCLK, SRESET, SMI Hold Time 3 ns 43 Note 5 t22 D31–D0, DP3–DP0, A31–A4 Read Setup Time 5 ns 43, 44 t23 D32–D0, DP3–DP0, A31–A4 Read Hold Time 3 ns 43, 44 Notes: 1. Specifications assume CL = 50 pF. I/O Buffer model must be used to determine delays due to loading (trace and component). First Order I/O buffer models for the processor are available. 2. 0-MHz operation guaranteed during stop clock operation. 3. Not 100% tested. Guaranteed by design characterization. 4. For faster transitions (>0.1% between adjacent clocks), use the Stop Clock protocol to switch operating frequency. 5. All timings are referenced at 1.5 V (as illustrated in the listed figures) unless otherwise noted. |
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