AM486DX2 datasheet(47/67 Pages) AMD

47 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

7.7.3

Auto HALT Restart

The Auto HALT Restart slot at register offset (word lo-

cation) 7F02h in SMRAM indicates to the SMI handler

that the SMI interrupted the CPU during a HALT state;

bit 0 of slot 7F02h is set to 1 if the previous instruction

was a HALT (see Figure 28). If the SMI did not interrupt

the CPU in a HALT state, then the SMI microcode sets

bit 0 of the Auto HALT Restart slot to 0. If the previous

instruction was a HALT, the SMI handler can choose to

either set or reset bit 0. If this bit is set to 1, the RSM

microcode execution forces the processor to re-enter

the HALT state. If this bit is set to 0 when the RSM

instruction is executed, the processor continues execu-

tion with the instruction just after the interrupted HALT

instruction. If the HALT instruction is restarted, the CPU

will generate a memory access to fetch the HALT in-

struction (if it is not in the internal cache), and execute

a HALT bus cycle.

Table 15 shows the possible restart configurations. If

the interrupted instruction was not a HALT instruction

(bit 0 is set to 0 in the Auto HALT Restart slot upon SMM

entry), setting bit 0 to 1 will cause unpredictable behavior

when the RSM instruction is executed.

7.7.4

I/O Trap Restart

The I/O instruction restart slot (register offset 7F00h in

SMRAM) gives the SMI handler the option of causing

the RSM instruction to automatically re-execute the in-

terrupted I/O instruction (see Figure 29).

When the RSM instruction is executed — if the I/O in-

struction restart slot contains the value 0FFh — the CPU

automatically re-executes the l/O instruction that the

SMI signal trapped. If the I/O instruction restart slot con-

tains the value 00h when the RSM instruction is execut-

ed, then the CPU does not re-execute the I/O instruction.

The CPU automatically initializes the I/O instruction re-

start slot to 00h during SMM entry. The I/O instruction

restart slot should be written only when the processor

has generated an SMI on an I/O instruction boundary.

Processor operation is unpredictable when the I/O in-

struction restart slot is set when the processor is servic-

ing an SMI that originated on a non-I/O instruction

boundary.

If the system executes back-to-back SMI requests, the

second SMI handler must not set the I/O instruction re-

start slot. The second back-to-back SMI signal will not

have the I/O Trap Word set.

7.7.5

I/O Trap Word

The I/O Trap Word contains the address of the I/O ac-

cess that forced the external chipset to assert SMI,

whether it was a read or write access, and whether the

instruction that caused the access to the I/O address

was a valid I/O instruction. Table 16 shows the layout.

Bits 31–16 contain the I/O address that was being ac-

cessed at the time SMI became active. Bits 15–2 are

reserved.

If the instruction that caused the I/O trap to occur was

a valid I/O instruction (IN, OUT, INS, OUTS, REP INS,

or REP OUTS), the Valid I/O Instruction bit is set. If it

was not a valid I/O instruction, the bit is saved as a 0.

For REP instructions, the external chip set should return

a valid SMI within the first access.

Bit 0 indicates whether the opcode that was accessing

the I/O location was performing either a read (1) or a

write (0) operation as indicated by the R/W bit.

Table 15. HALT Auto Restart Configuration

Value at

Entry

Value

at Exit

Processor Action on Exit

Return to next instruction in interrupted

program

Unpredictable

Returns to instruction after HALT

Returns to interrupted HALT instruction

HALT Auto Restart

Reserved

Figure 28. Auto HALT Restart Register Offset

Table 16. I/O Trap Word Configuration

31–16

15–2

I/O Address

Reserved

Valid I/O Instruction

R/W

I/O instruction restart slot

Figure 29. I/O Instruction Restart Register Offset

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