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AM486DX2 数据表(PDF) 12 Page - Advanced Micro Devices |
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AM486DX2 数据表(HTML) 12 Page - Advanced Micro Devices |
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12 / 67 page ![]() 12 Am5X86 Microprocessor AMD PRELIMINARY 2 LOGIC SYMBOL DP3–DP0 A31–A4 CLK A20M M/IO Am5X86 CPU W/R D/C 28 2 LOCK 4 BE3–BE0 Clock Address Bus Bus Cycle Definition Address PLOCK BS8 BS16 ADS RDY Bus Cycle Control 32 4 INTR NMI RESET Interrupts PCHK A3–A2 BRDY BLAST PWT PCD KEN FLUSH EADS AHOLD Data Parity Data Bus Burst Control Page Cacheability Invalidation Cache Control/ D31–D0 TMS TDI TDO TCK IEEE Test Port Access FERR IGNNE Numeric Error Reporting Bus Arbitration BREQ HOLD HLDA BOFF CACHE CLKMUL Clock Multiplier Mask HITM INV SMI SMIACT SMM SRESET STPCLK Stop Clock UP Upgrade VOLDET Voltage Detect Present WB/WT |
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