AM486DX2 datasheet(42/67 Pages) AMD

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Am5X86 Microprocessor

AMD

PRELIMINARY

CLK

CLK2

SMI

SMIACT

ADS

RDY

Normal State

State

Save

SMM

Handler

State

Restore

Normal

State

Clock-Tripled CPU

Clock-Quadrupled CPU

A: Last RDY from non-SMM transfer to SMIACT assertion

2 CLKs minimum

B: SMIACT assertion to first ADS for SMM state save

15 CLKs minimum

10 CLKs minimum

C: SMM state save (dependent on memory performance)

100 CLKs

70 CLKs

D: SMI handler

User-determined

E: SMM state restore (dependent on memory performance)

180 CLKs

120 CLKs

F: Last RDY from SMM transfer to deassertion of SMIACT

2 CLKs minimum

G: SMIACT deassertion of first non-SMM ADS

20 CLKs minimum

Figure 25. SMIACT Timing

7.3.3

SMRAM

The CPU uses the SMRAM space for state save and

state restore operations during an SMI. The SMI han-

dler, which also resides in SMRAM, uses the SMRAM

space to store code, data, and stacks. In addition, the

SMI handler can use the SMRAM for system manage-

ment information such as the system configuration, con-

figuration of a powered-down device, and system

designer-specific information.

Note: Access to SMRAM is through the CPU internal

cache. To ensure cache consistency and correct oper-

ation, always assert the FLUSH pin in the same clock

as SMI for systems using overlaid SMRAM.

The CPU asserts SMIACT to indicate to the memory

controller that it is operating in System Management

mode. The system logic should ensure that only the

CPU and SMI handler have access to this area. Alter-

nate bus masters or DMA devices trying to access the

SMRAM space when SMIACT is active should be di-

rected to system RAM in the respective area. The sys-

tem logic is minimally required to decode the physical

memory address range 38000h–3FFFFh as SMRAM

area. The CPU saves its state to the state save area

from 3FFFFh downward to 3FE00h. After saving its

state, the CPU jumps to the address location 38000h to

begin executing the SMI handler. The system logic can

choose to decode a larger area of SMRAM as needed.

The size of this SMRAM can be between 32 Kbytes and

4 Gbytes.The system logic should provide a manual

method for switching the SMRAM into system memory

space when the CPU is not in SMM. This enables ini-

tialization of the SMRAM space (i.e., loading SMI han-

dler) before executing the SMI handler during SMM (see

Figure 26).

SMRAM

System memory

accesses redirected

to SMRAM

System memory

accesses not

redirected to SMRAM

CPU

accesses to

system

address

space used

for loading

SMRAM

Normal

Memory

Space

Figure 26. Redirecting System Memory

Address to SMRAM

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