C5C5EDELTA-RMSLASHD datasheet(31/114 Pages) NXP

31 / 114 page

Pin Descriptions Grouped by Function

Clock Signals

Table 6 describes the C-3e NP clock signals.

CP Interface Signals

The C-3e NP’s 8 external CPs support various network physical interfaces, providing a

serial interface to the PHY layer. Interfaces are configured via bits in the C-3e NP register

set. Many interfaces are possible by programming the configuration registers. CPs can be

used individually or in a cluster (four CPs) to implement the various interfaces.

Table 7 provides a quick reference of all the CP pins organized by clusters. There are seven

physical I/O pins associated with each CP. All pins are capable of receiving data, with some

configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can

be configured as differential pairs for LVPECL compatibility.

In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally

configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four

CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for

receive and four for transmit) or four CPs that share the transmit and receive functions for

non-wire speed applications.

During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial

Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the

SDPs, with each getting access to the necessary I/O pins.

Table 6 Clock and Reference Signals

SIGNAL NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

SCLK*

SCLKX*

* SCLK and SCLKX must not be AC-coupled.

F14

F15

LVPECL

Core Clock Rate (Differential)

CCLK0

F16

LVTTL

Programmable CP Clock Input

CCLK1

E16

LVTTL

Programmable CP Clock Input

CCLK2

E15

LVTTL

Programmable CP Clock Input

CCLK3

E14

LVTTL

Programmable CP Clock Input

CPREF†

† If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must

be wired to an external reference, as specified in Table 34 on page 73. If none of the CPs are configured for

LVPECL operation, then the CPREF pin can be left unconnected.

D16

LVPECL

Reference

TOTAL

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

C5C5EDELTA-RM/D 数据表(PDF) 31 Page - NXP Semiconductors

C5C5EDELTA-RM/D 数据表(HTML) 31 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

C5C5EDELTA-RM/D 数据表(PDF) 31 Page - NXP Semiconductors

C5C5EDELTA-RM/D 数据表(HTML) 31 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载