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C5C5EDELTA-RM/D 数据表(PDF) 98 Page - NXP Semiconductors

部件名 C5C5EDELTA-RM/D
功能描述  C-3e Network Processor Silicon Revision A1
PDF  114 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

C5C5EDELTA-RM/D 数据表(HTML) 98 Page - NXP Semiconductors

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98
CHAPTER 3: ELECTRICAL SPECIFICATIONS
C3EN
QMU SRAM (Internal
Mode) Timing
Specifications
The QMU SRAM (Internal Mode) timing specifications are shown in Figure 26 and
described in Table 53.
Figure 26 QMU SRAM (Internal Mode) Timing Diagram
QACLKI
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Q_ctl
QAn
QDn
(output)
QDn
(input)
Tqc
Tqdo
Tqco
Tqao
Tqdv
Tqds
Tqdz
Tqdh
Table 53 QMU SRAM (Internal Mode) Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
COMMENT
Tqc
QMU Cycle Time
6.7
ns
Tqco
QMU Ctrl Output
0.8
4.4
ns
Loading is 50
Ω
transmission line.
Tqao
QMU Addr Output
0.8
4.4
ns
Loading is 50
Ω
transmission line.
Tqds
QMU Data Setup
0.8
ns
Tqdh
QMU Data Hold
0.8
ns
Tqdo
QMU Data Output
0.9
4.4
ns
Loading is 50
Ω
transmission line.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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