C5C5EDELTA-RMSLASHD datasheet(46/114 Pages) NXP

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CHAPTER 2: SIGNAL DESCRIPTIONS

C3EN

Figure 5 PROM Interface Diagram

The PROM interface operates in the following manner (Note that two accesses are

piplined together to execute one 32-bit fetch). The steps are shown in Figure 6.

1 The PROM_ADDR is loaded into the network processor internal shift register.

2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles.

3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external

presentation register.

4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit

PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift

5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external

presentation register and the first PROM_DATA into the external shift register.

6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network

processor internal shift register.

7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network

processor PROM_RETURN_DATA register and the second PROM_DATA into the

external shift register.

External Logic

PROM_ADDR<21:1>

PROM _H_Word

C-3e Network Processor

PROM Clock Gen.

PROM _Return_Data

PROM Sequencer

SPCLK

SPLD

SPDO

SPDI

Internal Shift

PROM_ADDR<21:1>

PROM _LO_Word

6 0

PROM

PROM_Data

External Shift

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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