C5C5EDELTA-RMSLASHD datasheet(35/114 Pages) NXP

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Pin Descriptions Grouped by Function

10/100 Ethernet (RMII) Configuration

Table 9 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface

(RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.

Table 9 10/100 Ethernet Signals

SIGNAL NAME*

PIN #

TOTAL

TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 7

LVTTL

REF_CLK

Transmit and Receive Clock (50MHz)

CPn_1

Table 7

LVTTL

CRS_DV

Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that

traffic is on the link, and is asserted if the signal is a 1 or an

alternating 1010... RX_DV indicates that a receive frame is in

progress and the data present on the RXD pins is valid. It is

asserted if this signal is a 1 for more than one cycle.

CPn_2

Table 7

LVTTL

OPD

TXD(0)

Transmit Data 0 (first on wire)

CPn_3

Table 7

LVTTL

TXD(1)

Transmit Data 1 (second on wire)

CPn_4

Table 7

LVTTL

RXD(0)

Receive Data 0 (first on wire)

CPn_5

Table 7

LVTTL

RXD(1)

Receive Data 1 (second on wire)

CPn_6

Table 7

LVTTL

TX_EN

Transmit Enable. When asserted, the data on TXD is encoded and

transmitted on the twisted pair cable.

TOTAL PINS

* n can be from 0 to 7. See Table 7.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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