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C5C5EDELTA-RM/D 数据表(PDF) 96 Page - NXP Semiconductors

部件名 C5C5EDELTA-RM/D
功能描述  C-3e Network Processor Silicon Revision A1
PDF  114 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

C5C5EDELTA-RM/D 数据表(HTML) 96 Page - NXP Semiconductors

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96
CHAPTER 3: ELECTRICAL SPECIFICATIONS
C3EN
TLU Timing Specifications
The TLU timing specifications are shown in Figure 25 and described in Table 51.
Figure 25 TLU Timing Diagram
TCLKI
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
T_ctl
TAn
TDn
(output)
TDn
(input)
Ttc
Ttdo
Ttco
Ttao
Ttdv
Ttds
Ttdz
Ttdh
Table 51 TLU Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Ttc
TLU Cycle Time
8.0
ns
Ttco
TLU Ctrl Output
0.8
3.9
ns
Ttao
TLU Addr Output
0.8
3.9
ns
Ttds
TLU Data Setup
1.0
ns
Ttdh
TLU Data Hold
1.2
ns
Ttdo
TLU Data Output
0.8
4.2
ns
Ttdz
TLU Data Clk to Tri*
* Not fully tested, values based on design/characterization.
0.8
4.2
ns
Ttdv
TLU Data Clk to Driven*
0.8
4.2
ns
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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