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C5C5EDELTA-RM/D 数据表(PDF) 54 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D 数据表(HTML) 54 Page - NXP Semiconductors |
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54 / 114 page  54 CHAPTER 2: SIGNAL DESCRIPTIONS C3EN QMU SRAM (Internal Mode) Interface Signals The QMU signals are described in Table 24. Table 24 QMU SRAM (Internal Mode) Interface Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION QA0 - QA16 D10, C10, A10, F11, E11, D11, C11, B11, A11, F12, E12, D12, C12, A12, F13, E13, D13 17 LVTTL O Address [16:0] QD0 - QD31 F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3, B3, A3, D4, B4, A4, E5, D5, C5, B5, A5, E6, C6, A6, E7, D7, C7, B7, A7, E8, D8 32 LVTTL I PD/O Data QDQPAR C8 1 LVTTL I PD nc QARDY F10 1 LVTTL I PD nc QNQRDY A9 1 LVTTL I PD nc QWEX E10 1 LVTTL O Write Enable QBCLKO B8 1 LVTTL O nc QBCLKI A8 1 LVTTL I PD nc QACLKO F9 1 LVTTL O nc QACLKI E9 1 LVTTL I PD Input Clock QDPL C9 1 LVTTL I PD/O Data Parity Low QDPH B9 1 LVTTL I PD/O Data Parity High TOTAL PINS 59 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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