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C5C5EDELTA-RM/D 数据表(PDF) 57 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D 数据表(HTML) 57 Page - NXP Semiconductors |
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57 / 114 page  Pin Descriptions Grouped by Function 57 03 Test Signals Test signals are described in Table 27. During JTAG, SCLK and SCLKX must remain as differential inputs. Table 27 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION JTCK B17 1 LVTTL I PD Test Clock JTMS A17 1 LVTTL I PD Test Mode Select. High selects modes as defined in the IEEE 1149.1 JTAG specification. JTRSTX A16 1 LVTTL I PD Test Reset (low active) JTDI C16 1 LVTTL I PD Test Data In JTDO C14 1 LVTTL O Test Data Out JHIGHZ B15 1 LVTTL I PD Turns off all output drivers when High JCLKBYP A15 1 LVTTL I PD 1X or 2X Clock Mode Select. Low selects 1X, High selects 2X. JSE D15 1 LVTTL I PD Scan Enable. High enables scan test. JS00-JS05 C13, B13, A13, B14, A14, C15 6 LVTTL O Scan Out Pins TOTAL PINS 14 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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