C5C5EDELTA-RMSLASHD datasheet(51/114 Pages) NXP

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Pin Descriptions Grouped by Function

BMU SDRAM Interface

Signals

The BMU and SDRAM interface signals are described in Table 22.

The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines

and all 12 address lines must be connected to the SDRAM in order for the BMU to be able

to read and write external SDRAM properly.

Table 22 BMU SDRAM Interface Signals

SIGNAL NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

MD0 - MD129

AA27, AA25, AA24, AA23, AA21,

AA20, Y27, Y26, Y25, Y23, Y22, Y21,

Y20, W27, W26, W25, W23, W22,

W21, W20, V27, V25, V24, V23, V21,

V20, U27, U26, U25, U24, U23, U22,

U21, U20, T27, T26, T25, T23, T22,

T21, T20, R27, R26, R25, R24, R23,

R22, R21, R20, P27, P25, P24, P23,

P21, P20, N27, N26, N25, N24, N23,

N22, N21, N20, M27, M26, M25,

M23, M22, M21, M20, L27, L26, L25,

L24, L23, L22, L21, L20, K27, K25,

K24, K23, K21, K20, J27, J26, J25,

J23, J22, J21, J20, H27, H26, H25,

H23, H22, H21, H20, G27, G25, G24,

G23, G21, G20, F27, F26, F25, F24,

F23, F22, F21, F20, E27, E26, E25,

E23, E22, E21, E20, D27, D25, D24,

D23, D21, D20, C27, C26, C25, C23,

C22

130

LVTTL

PD/O

Data Lines In

MDECC0 - MDECC8 A27, B20, B21, B23, B24, B25, B27,

C20, C21

LVTTL

PD/O

Stored as data, ECC bits

MA0 - MA11

C19, B19, A19, F18, E18, D18, C18,

A18, F17, E17, D17, C17

LVTTL

Address Outputs: A0-A11 are sampled during the

ACTIVE command and READ/WRITE to select one

location out of the memory array in the respective

bank. The address inputs also provide the

op-code during a LOAD MODE REGISTER

command

MBA0 - MBA1

F19, E19

LVTTL

Bank Address Outputs: BA0 and BA1 define which

bank the ACTIVE, READ, WRITE or PRECHARGE

command is being applied

MCASX

A24

LVTTL

Command Outputs: MRASX, MCASX, MWEX and

MCSX define the command being entered.

NOTE: MCSX is considered part of the command

code.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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