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C5C5EDELTA-RM/D 数据表(PDF) 48 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D 数据表(HTML) 48 Page - NXP Semiconductors |
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48 / 114 page  48 CHAPTER 2: SIGNAL DESCRIPTIONS C3EN General System Interface Signal Table 18 provides the signal for the Executive Processor reset power status and I/O clock. The C-3e NP can be powered up with the XP either running or with the XP in reset mode similar to the CPs. When the XP remains in reset mode, an external host can be used to control the initialization of the C-3e NP. Table 18 General System Interface Signal SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION XPUHOT Y3 1 LVTTL I PD Sample at Power On Reset determines if the XP RISC Core is held in reset. Low equals reset and High equals active. During normal operation, this is an external interrupt. TOTAL PINS 1 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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