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C5C5EDELTA-RM/D 数据表(PDF) 40 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D 数据表(HTML) 40 Page - NXP Semiconductors |
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40 / 114 page  40 CHAPTER 2: SIGNAL DESCRIPTIONS C3EN SONET OC-3 Transceiver Interface Configuration Table 13 describes the SONET Optical Carrier (OC) 3 transceiver interface signals. For each CP (0-15), you can implement a single OC-3 interface. Table 13 OC-3 Signals SIGNAL NAME* PIN #† TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn_0 Table 7 1 LVPECL I PD RCLK_H Receive Clock noninverted side of pair (155.52MHz) CPn_1 Table 7 1 LVPECL I PU RCLK_L Receive Clock inverted side of pair (155.52MHz) CPn_2 Table 7 1 LVPECL O PD TXD_H Transmit Data noninverted side of pair CPn_3 Table 7 1 LVPECL I PU TXD_L Transmit Data inverted side of pair CPn_4 Table 7 1 LVPECL IPD RXD_H Receive Data noninverted side of pair CPn_5 Table 7 1 LVPECL I PU RXD_L Receive Data inverted side of pair CPn_6 Table 7 1 LVPECL I PU SIGNAL_DET A light level above a certain threshold is present at the optical receiver - single ended LVPECL. TOTAL PINS 7 * n can be from 0 to 7. † Reference Table 7 for pin numbers for the actual cluster(s) you are configuring. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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