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C5C5EDELTA-RM/D 数据表(PDF) 80 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D 数据表(HTML) 80 Page - NXP Semiconductors |
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80 / 114 page  80 CHAPTER 3: ELECTRICAL SPECIFICATIONS C3EN Clock Timing Specifications The system clock timing is shown in Figure 13 and described in Table 37. Figure 13 System Clock Timing Diagram Tsc Tsh SCLK Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 SCLKX CCLKn TccN Tsl Tcch Tccl Table 37 System Clock Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT Tsc System Cycle Time 3.76 ns 180MHz core clock Tsh Sys Clk High Pulse 45 55 Duty cycle* * Pulse duty cycle measured at crossing voltage of SCLK/SCLKX Tsl Sys Clk Low Pulse 45 55 Duty cycle* Tcc0 CCLK0 Cycle Time 6.43 ns † † The frequencies specified for CCLK0 - CCLK3 allow full flexibility for the C-3e NP. It is also possible to use one or more CCLKn inputs for other frequencies; contact your Motorola representative for more information. Tcc1 CCLK1 Cycle Time 6.43 ns † Tcc2 CCLK2 Cycle Time 6.43 ns † Tcc3 CCLK3 Cycle Time 6.43 ns † Tcch CCLKm High Time 40% 60% % cycle pulse is high Tccl CCLKm Low Time 40% 60% % cycle pulse is low Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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