C5C5EDELTA-RMSLASHD datasheet(37/114 Pages) NXP

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Pin Descriptions Grouped by Function

Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example

SIGNAL NAME*

PIN #†

TOTAL

TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 7 1

LVTTL

T_CLK

GMII Transmit Clock (125MHz). This clock is used to synchronize the

transmit data.

CPn_1

Table 7 1

LVTTL

TCLKI

MII transmit clock. Transmit data aligned to this clock input from

phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT

CPn_2

Table 7 1

LVTTL

TXD(0)

Transmit Data (byte-wide data, least significant bit)

CPn_3

Table 7 1

LVTTL

TXD(1)

Transmit Data

CPn_4

Table 7 1

LVTTL

TXD(2)

Transmit Data

CPn_5

Table 7 1

LVTTL

TXD(3)

Transmit Data

CPn_6

Table 7 1

LVTTL

TX_EN

Transmit Enable. When asserted, the data on TXD is encoded and

transmitted on the twisted pair cable.

CPn+1_0

Table 7 1

CPn+1_1

Table 7 1

LVTTL

COL

Collision. Asserted when both RX_DV and TX_EN are valid during

half duplex operation.

CPn+1_2

Table 7 1

LVTTL

TXD(4)

Transmit Data

CPn+1_3

Table 7 1

LVTTL

TXD(5)

Transmit Data

CPn+1_4

Table 7 1

LVTTL

OPD

TXD(6)

Transmit Data

CPn+1_5

Table 7 1

LVTTL

TXD(7)

Transmit Data (byte-wide receive data, most significant bit)

CPn+1_6

Table 7 1

LVTTL

TX_ER

Transmit Error. Asserting TX_ER when TX_EN is a 1 causes

transmission of the designated “bad code” in lieu of the normal

encoded data on the twisted pair data.

CPn+2_0

Table 7 1

CPn+2_1

Table 7 1

LVTTL

IPU

RCLK

Receive Clock (125MHz)

CPn+2_2

Table 7 1

LVTTL

RXD(0)

Receive Data (byte-wide receive data, least significant bit)

CPn+2_3

Table 7 1

LVTTL

RXD(1)

Receive Data

CPn+2_4

Table 7 1

LVTTL

IPD

RXD(2)

Receive Data

CPn+2_5

Table 7 1

LVTTL

RXD(3)

Receive Data

CPn+2_6

Table 7 1

LVTTL

RX_DV

Receive Data Valid. Indicates that there is a receive frame in progress

and that the data present on the RXD signals is valid.

CPn+3_0

Table 7 1

CPn+3_1

Table 7 1

LVTTL

CRS

Carrier Sense. Indicates traffic is on the link. CRS is asserted when a

non-idle condition is detected on the receive data stream. CRS is

deasserted when an end of frame or idle condition is detected.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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