C5C5EDELTA-RMSLASHD datasheet(39/114 Pages) NXP

39 / 114 page

Pin Descriptions Grouped by Function

CPn+1_3

Table 7 1

LVTTL

TXD(4)

Transmit Data

CPn+1_4

Table 7 1

LVTTL

TXD(3)

Transmit Data

CPn+1_5

Table 7 1

LVTTL

TXD(2)

Transmit Data

CPn+1_6

Table 7 1

LVTTL

TXD(0)

Transmit Data (ten bits wide, first on wire)

CPn+2_0

Table 7 1

CPn+2_1

Table 7 1

LVTTL

RCLK

Receive Clock (62.5 MHz)

CPn+2_2

Table 7 1

LVTTL

RXD(9)

Receive Data (ten bits wide, last on wire)

CPn+2_3

Table 7 1

LVTTL

RXD(8)

Receive Data

CPn+2_4

Table 7 1

LVTTL

IPD

RXD(7)

Receive Data

CPn+2_5

Table 7 1

LVTTL

RXD(6)

Receive Data

CPn+2_6

Table 7 1

LVTTL

RXD(1)

Receive Data

CPn+3_0

Table 7 1

ncPD

CPn+3_1

Table 7 1

LVTTL

RCLKN

Receive Clock Inverted

CPn+3_2

Table 7 1

LVTTL

RXD(5)

Receive Data

CPn+3_3

Table 7 1

LVTTL

IPU

RXD(4)

Receive Data

CPn+3_4

Table 7 1

LVTTL

RXD(3)

Receive Data

CPn+3_5

Table 7 1

LVTTL

RXD(2)

Receive Data

CPn+3_6

Table 7 1

LVTTL

IPU

RXD(0)

Receive Data (ten bits wide, first on wire)

TOTAL PINS

* n can be 0, or 4.

† Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.

Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued)

SIGNAL NAME*

PIN #†

TOTAL

TYPE

I/O

LABEL

SIGNAL DESCRIPTION

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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