C5C5EDELTA-RMSLASHD datasheet(34/114 Pages) NXP

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CHAPTER 2: SIGNAL DESCRIPTIONS

C3EN

DS1/T1 Framer Interface Configuration

Table 8 describes the serial framer interface signals. For each CP (0-7), you can implement

one serial Framer interface.

CP3_5

AG22

CP7_5

AC17

CP3_6

AE22

CP7_6

AB17

Table 7 CP Physical Interface Signals and Pins (Grouped by Clusters) (continued)

CP CLUSTER 1

CP CLUSTER 2

SIGNAL

PIN #

SIGNAL

PIN #

Table 8 DS1/T1 Framer Interface Signals

SIGNAL NAME*

PIN #†

TOTAL

TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 7

LVTTL

TCLK

Transmit Clock (1.544MHz)

CPn_1

Table 7

LVTTL

RCLK

Receive Clock (1.544MHz)

CPn_2

Table 7

LVTTL

TData

Transmit Data

CPn_3

Table 7

LVTTL

TFrame

Transmit Frame Synchronization

CPn_4

Table 7

LVTTL

IPD

RData

Receive Data

CPn_5

Table 7

LVTTL

RFrame

Receive Frame Synchronization

CPn_6

Table 7

TOTAL PINS

* n can be from 0 to 7. See Table 7.

† Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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