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C5C5EDELTA-RM/D 数据表(PDF) 55 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D 数据表(HTML) 55 Page - NXP Semiconductors |
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55 / 114 page  Pin Descriptions Grouped by Function 55 03 QMU to Q-5/Q-3 (External Mode) Interface Signals The QMU to Q-5/Q-3 signals are described in Table 25. Table 25 QMU to Q-5/Q-3 (External Mode) Interface Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION QA0 - QA15 D10, C10, A10, F11, E11, D11, C11, B11, A11, F12, E12, D12, C12, A12, F13, E13 16 LVTTL O Enqueue Data [8:23] QA16 D13 1 LVTTL O Enqueue Parity QD0 - QD23 F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3, B3, A3, D4, B4, A4, E5, D5, C5, B5, A5, E6, C6 24 LVTTL I PD Dequeue Data [0:23] QD24 - QD31 A6, E7, D7, C7, B7, A7, E8, D8 8 LVTTL I PD Enqueue Data [0:7] QDQPAR C8 1 LVTTL I PD Dequeue Parity QARDY F10 1 LVTTL I PD Dequeue Ack Ready QNQRDY A9 1 LVTTL O Enqueue Ready QWEX E10 1 LVTTL O Dequeue Ready QBCLKO B8 1 LVTTL O Output ClockB QBCLKI A8 1 LVTTL I PD Input ClockB QACLKO F9 1 LVTTL O Output ClockA QACLKI E9 1 LVTTL I PD Input ClockA QDPL C9 1 LVTTL O Dequeue Ack [0] QDPH B9 1 LVTTL O Dequeue Ack [1] TOTAL PINS 59 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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