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C5C5EDELTA-RM/D 数据表(PDF) 101 Page - NXP Semiconductors

部件名 C5C5EDELTA-RM/D
功能描述  C-3e Network Processor Silicon Revision A1
PDF  114 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

C5C5EDELTA-RM/D 数据表(HTML) 101 Page - NXP Semiconductors

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AC Timing Specifications
101
03
Table 55 QMU to Q-5/Q-3 (External Mode) Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
COMMENT
Tqec
QMU External Cycle Time
10.0
ns
QACLKO/QBCLKO
derived from
QACLKI/QBCLKI
Tqep
QMU CLKA-CLKB delta
between rising edges
4.8
ns
Tqes
QMU Input Data Setup
0.6
ns
Tqeh
QMU Input Data Hold
0.8
ns
Tqeo
QMU Data Output
-.85
1.3
ns
Determines valid time
for data from each clock
rising edge
Table 56 Signal Groups in QMU to Q-5/Q-3 (External Mode) Timimg Diagrams
SIGNAL GROUP
INCLUDED SIGNALS
Input Clocks (QnCLKI)
QACLKI, QBCLKI
Output Clocks (QnCLKO)
QACLKO, QBCLKO
Input Data (DQDATA)
QD0-23, QARDY, QDPL, QDPH, QNQRDY, QDQPAR
Output Data (NQDATA)
QA0-16, QWEX, QD24-31
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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