STM32H7B3AI datasheet(5/238 Pages) STMICROELECTRONICS

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Description

STM32H7B3xI devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to

280 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE

754 compliant) and single-precision data-processing instructions and data types. STM32H7B3xI devices support

a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.

STM32H7B3xI devices incorporate high-speed embedded memories with a dual-bank flash memory of 2 Mbytes,

around 1.4 Mbyte of RAM (including 192 Kbytes of TCM RAM, 1.18 Mbytes of user SRAM and 4 Kbytes of

backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to four APB buses,

three AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and

external memory access.

All the devices offer two ADCs, two DACs (one dual and one single DAC), two ultra-low power comparators, a

low-power RTC, 12 general-purpose 16-bit timers, two PWM timers for motor control, three low-power timers,

a true random number generator (RNG), and a cryptographic acceleration cell and a HASH processor. The

devices support nine digital filters for external sigma delta modulators (DFSDM). They also feature standard and

advanced communication interfaces.

•

Standard peripherals

–

Four I2Cs

–

Five USARTs, five UARTs and one LPUART

–

Six SPIs, four I2Ss in full-duplex mode. To achieve audio class accuracy, the I2S peripherals can be

clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.

–

Two SAI serial audio interfaces, out of which one with PDM

–

One SPDIFRX interface

–

One single wire protocol master interface (SWPMI)

–

One 16-bit parallel synchronous slave interface (PSSI) sharing the same interface as the digital

camera)

–

Management Data Input/Output (MDIO) slaves

–

Two SDMMC interfaces (one can be supplied from a supply voltage separate from that of all other I/Os)

–

A USB OTG high-speed with full-speed capability (with the ULPI)

–

One FDCAN plus one TT-CAN interface

–

Chrom-ART Accelerator

–

HDMI-CEC

•

Advanced peripherals including

–

A flexible memory control (FMC) interface

–

Two octo-SPI memory interface with on-the-fly decryption (OTFDEC)

–

A digital camera interface for CMOS sensors (DCMI)

–

A graphic memory management unit (GFXMMU)

–

An LCD-TFT display controller (LTDC)

–

A JPEG hardware compressor/decompressor

Refer to Table 1. STM32H7B3xI features and peripheral counts for the list of peripherals available on each part

number.

STM32H7B3xI devices operate in the –40 to +85 °C ambient temperature range from a 1.62 to 3.6 V

power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see

Section 3.5.2 Power supply supervisor) and connecting the PDR_ON pin to VSS. Otherwise the supply voltage

must stay above 1.71 V with the embedded power voltage detector enabled.

The USB OTG_HS/FS interfaces can be supplied either by the integrated USB regulator or through a separate

supply input.

A dedicated supply input is available for one of the SDMMC interface for package with more than 100 pins. It

allows running from a different voltage level than all other I/Os.

A comprehensive set of power-saving mode allows the design of low-power applications.

The CPU and domain states can be directly monitored on some GPIOs configured as alternate functions.

STM32H7B3xI devices are offers in several packages ranging from 64 pins to 225 pins/balls. The set of included

peripherals changes with the device chosen.

STM32H7B3xI

Description

DS13139 - Rev 8

page 5/238

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