STM32H7B3AI datasheet(23/238 Pages) STMICROELECTRONICS

23 / 238 page

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three DAC converters: one for each output channel

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8-bit or 12-bit monotonic output

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left or right data alignment in 12-bit mode

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synchronized update capability

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noise-wave generation

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triangular-wave generation

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Triple DAC channel independent or simultaneous conversions

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DMA capability for each channel including DMA underrun error detection

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external triggers for conversion

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input voltage reference VREF+ or internal VREFBUF reference.

The DAC channels are triggered through the timer update outputs that are also connected to different DMA

streams.

3.23

Voltage reference buffer (VREFBUF)

The built-in voltage reference buffer can be used as voltage reference for ADCs and DACs, as well as voltage

reference for external components through the VREF+ pin.

Five different voltages are supported (refer to the reference manual for details).

3.24

Ultra-low-power comparators (COMP)

The STM32H7B3xI devices embed two rail-to-rail comparators (COMP1 and COMP2). They feature

programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) as well as

selectable output polarity.

The reference voltage can be one of the following:

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An external I/O

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A DAC output channel

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An internal reference voltage or submultiple (1/4, 1/2, 3/4)

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The analog temperature sensor

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The VBAT/4 supply.

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers, and be combined

into a window comparator.

3.25

Operational amplifiers (OPAMP)

The STM32H7B3xI devices embed two rail-to-rail operational amplifiers (OPAMP1 and OPAMP2) with external

or internal follower routing and PGA capability, and two inputs and one output each. These three I/Os can be

connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers

can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with

inverting gain ranging from -1 to -15.

The operational amplifier main features are:

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PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3, -7 or -15

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Up to two positive inputs connected to DAC

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Output connected to internal ADC

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Low input bias current down to 1 nA

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Low input offset voltage down to 1.5 mV

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Gain bandwidth up to 8 MHz

The devices embed two operational amplifiers (OPMAP1 and OPAMP2) with two inputs and one output each.

These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The

operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging

from 2 to 16 or with inverting gain ranging from -1 to -15.

3.26

Digital filter for sigma-delta modulators (DFSDM)

The device embeds two DFSDM interfaces:

STM32H7B3xI

Voltage reference buffer (VREFBUF)

DS13139 - Rev 8

page 23/238

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