STM32H7B3AI datasheet(26/238 Pages) STMICROELECTRONICS

26 / 238 page

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Up to four programmable quantization tables

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Fully programmable Huffman tables (two AC and two DC)

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Fully programmable minimum coded unit (MCU)

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Encode/decode support (non simultaneous)

•

Single clock Huffman coding and decoding

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Two-channel interface: Pixel/Compress In, Pixel/Compressed Out

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Stallable design

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Support for single greyscale component

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Ability to enable/disable header processing

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Internal register interface

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Fully synchronous design

•

Configuration for high-speed decode mode

3.31

True random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. The

RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It

is composed of a live entropy source (analog) and an internal conditioning component.

3.32

Cryptographic acceleration (CRYP and HASH)

The devices embed a cryptographic processor that supports the advanced cryptographic algorithms usually

required to ensure confidentiality, authentication, data integrity and non-repudiation when exchanging messages

with a peer:

•

Encryption/Decryption

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DES/TDES (data encryption standard/triple data encryption standard): ECB (electronic codebook) and

CBC (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key

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AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter mode) chaining

algorithms, 128, 192 or 256-bit key

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Universal HASH

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SHA-1 and SHA-2 (secure HASH algorithms)

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MD5

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HMAC

The cryptographic accelerator supports DMA request generation.

3.33

On-the-fly decryption engine (OTFDEC)

The embedded OTFDEC decrypts in real-time the encrypted content stored in the external Octo-SPI memories

used in Memory-mapped mode.

The OTFDEC uses the AES-128 algorithm in counter mode (CTR).

Code execution on external Octo-SPI memories can be protected against fault injection thanks to

STMicroelectronics enhanced encryption mode (refer to RM0455 for details).

The OTFDEC main features are as follow:

•

On-the-fly 128-bit decryption during STM32 Octo-SPI read operations (single or multiple).

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AES-CTR algorithm with keystream FIFO (depth= 4)

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Support for any read size

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Up to four independent encrypted regions

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Region definition granularity: 4096 bytes

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Region configuration write locking mechanism

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Two optional decryption modes: execute-only and execute-never

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128-bit key for each region, two-byte firmware version, and eight-byte application-defined nonce

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Encryption keys confidentiality and integrity protection

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Write only registers with software locking mechanism

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Availability of 8-bit CRC as public key information

STM32H7B3xI

True random number generator (RNG)

DS13139 - Rev 8

page 26/238

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