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STM32H7B3AI 数据表(PDF) 68 Page - STMicroelectronics |
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STM32H7B3AI 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 238 page  Pin/ball name(1) (2) Pin name (function after reset) Pin type I/O structure Alternate functions Additional functions - - - - - - - - - - - - K7 - - VSS S - - - 1. The devices with SMPS correspond to commercial code STM32H7B3xIxxQ. 2. A non-connected I/O in a given package is configured as an output tied to VSS. Any analog peripheral connected to such a pad (such as OPAMP, VREF+) must be disabled. 3. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits. 4. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits. STM32H7B3xI Pin descriptions DS13139 - Rev 8 page 68/238 |
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