STM32H7B3AI datasheet(33/238 Pages) STMICROELECTRONICS

33 / 238 page

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Able to operate in and wake up from STOP mode

3.45

SD/SDIO/MMC card host interfaces (SDMMC)

Two SDMMC host interfaces are available. They support MultiMediaCard System Specification version 4.51 in

three different databus modes: 1 bit (default), 4 bits and 8 bits.

One of the SDMMC interface can be supplied through a separate VDDMMC supply. If required, it can thus operate

at a different voltage level than all other I/Os.

Both interfaces support the SD memory card specifications version 4.1. and the SDIO card specification version

4.0. in two different databus modes: 1 bit (default) and 4 bits.

Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a stack of MMC Version

4.51 or previous.

The SDMMC host interface embeds a dedicated DMA controller allowing high-speed transfers between the

interface and the SRAM.

3.46

Controller area network (FDCAN1, FDCAN2)

The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory

and a clock calibration unit.

Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol specification version

2.0 part A, B) and CAN FD protocol specification version 1.0.

FDCAN1 supports time triggered CAN (TTCAN) specified in ISO 11898-4, including event synchronized

time-triggered communication, global system time, and clock drift compensation. FDCAN1 contains additional

registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and

time-triggered CAN communication.

A 10 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs,

transmit buffers (and triggers for TTCAN). This message RAM is shared between the two FDCAN1 and FDCAN2

modules.

The common clock calibration unit is optional. It can be used to generate a calibrated clock for both FDCAN1 and

FDCAN2 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1.

3.47

Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral that supports both

full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and a

UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG_HS interface in

HS mode, an external PHY device connected to the ULPI is required.

The USB OTG_HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification.

It features software-configurable endpoint setting and supports suspend/resume. The USB OTG_HS controller

requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.

The main features are:

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Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing

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Supports the session request protocol (SRP) and host negotiation protocol (HNP)

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8 bidirectional endpoints

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16 host channels with periodic OUT support

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Software configurable to OTG1.3 and OTG2.0 modes of operation

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USB 2.0 LPM (Link Power Management) support

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Battery Charging Specification Revision 1.2 support

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Internal FS OTG PHY support

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External HS or HS OTG operation supporting ULPI in SDR mode

The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the

60 MHz output.

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Internal USB DMA

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HNP/SNP/IP inside (no need for any external resistor)

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For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

STM32H7B3xI

SD/SDIO/MMC card host interfaces (SDMMC)

DS13139 - Rev 8

page 33/238

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