STM32H7B3AI datasheet(24/238 Pages) STMICROELECTRONICS

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DSFDM1

It is located in the CD domain and features eight external digital serial interfaces (channels) and eight digital

filters, or alternately eight internal parallel inputs.

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DSFDM2

It is located in the SRD domain. DFSDM2 is a lite version including two external digital serial interfaces

(channels) and one digital filters.

The DFSDM peripherals interface the external Σ∆ modulators to microcontroller and then perform digital filtering

of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDMs can also interface

PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware.

The DFSDMs feature optional parallel data stream inputs from internal ADC peripherals or microcontroller

memory (through DMA/CPU transfers into DFSDM).

DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital

filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC

resolution.

The DFSDM peripherals support:

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Multiplexed input digital serial channels:

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configurable SPI interface to connect various SD modulator(s)

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configurable Manchester coded 1 wire interface support

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PDM (Pulse Density Modulation) microphone input support

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maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

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clock output for SD modulator(s): 0..20 MHz

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Alternative inputs from eight internal digital parallel channels (up to 16 bit input resolution):

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internal sources: ADC data or memory data streams (DMA)

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Digital filter modules with adjustable digital signal processing:

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Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)

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integrator: oversampling ratio (1..256)

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Up to 24-bit output data resolution, signed output data format

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Automatic data offset correction (offset stored in register by user)

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Continuous or single conversion

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Start-of-conversion triggered by:

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software trigger

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internal timers

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external events

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start-of-conversion synchronously with first digital filter module (DFSDM0)

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Analog watchdog feature:

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low value and high value data threshold registers

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dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)

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input from final output data or from selected input digital serial channels

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continuous monitoring independently from standard conversion

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Short circuit detector to detect saturated analog input values (bottom and top range):

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up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream

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monitoring continuously each input serial channel

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Break signal generation on analog watchdog event or on short circuit detector event

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Extremes detector:

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storage of minimum and maximum values of final conversion data

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refreshed by software

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DMA capability to read the final conversion data

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Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence

STM32H7B3xI

Digital filter for sigma-delta modulators (DFSDM)

DS13139 - Rev 8

page 24/238

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