STM32H7B3AI datasheet(14/238 Pages) STMICROELECTRONICS

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3.4

Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to

program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes:

•

All flash address space

•

All RAM address space: ITCM, DTCM RAMs and SRAMs

•

The system memory bootloader

The boot loader is located in non-user System memory. It is used to reprogram the flash memory through a serial

interface (USART, I2C, SPI, USB-DFU, FDCAN). Refer to STM32 microcontroller system memory boot mode

application note (AN2606) for details.

3.5

Power supply management

3.5.1

Power supply scheme

•

VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD pins.

•

VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE

•

VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL.

•

VDD33USB and VDD50USB:

VDD50USB can be supplied through the USB cable to generate the VDD33USB via the USB internal regulator. This

allows supporting a VDD supply different from 3.3 V.

The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.

•

VDDMMC = 1.62 to 3.6 V external power supply for independent I/Os. VDDMMC can be higher than VDD.

VDDMMC pin should be tied to VDD when it is not used.

•

VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.

•

VCAP: VCORE supply, which value depends on voltage scaling (0.74 V, 0.9 V, 1.0 V, 1.1 V, 1.2 V or 1.3 V). It

is configured through VOS bits in PWR_CR3 register. The VCORE domain is split into two domains the CPU

domain (CD) and the Smart Run Domain (SRD).

–

CD domain containing most of the peripherals and the Arm® Cortex®-M7 core

–

SRD domain containing some peripherals and the system control.

•

VDDSMPS = 1.62 to 3.6 V: step-down converter power supply

•

VLXSMPS = VCORE or 1.8 to 2.5 V: external regulated step-down converter output

•

VFBSMPS = VCORE or 1.8 to 2.5 V: external step-down converter feedback voltage sense input

Note:

For I/O speed optimization at low VDD supply, refer to Section 3.8 General-purpose input/outputs (GPIOs).

The features available on the device depend on the package (refer to Table 1. STM32H7B3xI features and

peripheral counts).

During power-up and power-down phases, the following power sequence requirements must be respected (see

Figure 2. Power-up/power-down sequence):

•

When VDD is below 1 V, other power supplies (VDDA, VDD33USB and VDD50USB) must remain below VDD +

300 mV.

•

When VDD is above 1 V, all power supplies are independent (except for VDDSMPS, which must remain at the

same level as VDD).

During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided

to the microcontroller remains below 1 mJ. This allows external decoupling capacitors to be discharged with

different time constants during the power-down transient phase.

STM32H7B3xI

Boot modes

DS13139 - Rev 8

page 14/238

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