STM32H7B3AI datasheet(32/238 Pages) STMICROELECTRONICS

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3.41

Serial audio interfaces (SAI)

The devices embed two SAIs (SAI1, SAI2) that allow designing many stereo or mono audio protocols such as

I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available when the audio block is

configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent

audio sub-blocks. Each block has it own clock generator and I/O line controller.

Audio sampling frequencies up to 192 kHz are supported.

One of the SAI supports up to 8 microphones thanks to an embedded PDM interface.

The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and

can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other

SAIs to work synchronously.

3.42

SPDIFRX receiver interface (SPDIFRX)

The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These

standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound,

such as those defined by Dolby or DTS (up to 5.1).

The main SPDIFRX features are the following:

•

Up to 4 inputs available

•

Automatic symbol rate detection

•

Maximum symbol rate: 12.288 MHz

•

Stereo stream from 32 to 192 kHz supported

•

Supports Audio IEC-60958 and IEC-61937, consumer applications

•

Parity bit management

•

Communication using DMA for audio samples

•

Communication using DMA for control and user channel information

•

Interrupt capabilities

The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming

data stream. The user can select the wanted SPDIF input, and when a valid signal will be available, the SPDIFRX

will re-sample the incoming signal, decode the Manchester stream, recognize frames, sub-frames and blocks

elements. It delivers to the CPU decoded data, and associated status flags.

The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that will

be used to compute the exact sample rate for clock drift algorithms.

3.43

Single wire protocol master interface (SWPMI)

The single wire protocol master interface (SWPMI) is the master interface corresponding to the contactless

frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are:

•

full-duplex communication mode

•

automatic SWP bus state management (active, suspend, resume)

•

configurable bit rate up to 2 Mbit/s

•

automatic SOF, EOF and CRC handling

SWPMI can be served by the DMA controller.

3.44

Management data input/output (MDIO) slaves

The devices embed an MDIO slave interface it includes the following features:

•

32 MDIO register addresses, each of which is managed using separate input and output data registers:

–

32 x 16-bit firmware read/write, MDIO read-only output data registers

–

32 x 16-bit firmware read-only, MDIO write-only input data registers

•

Configurable slave (port) address

•

Independently maskable interrupts/events:

–

MDIO register write

–

MDIO register read

–

MDIO protocol error

STM32H7B3xI

Serial audio interfaces (SAI)

DS13139 - Rev 8

page 32/238

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