STM32H7B3AI datasheet(10/238 Pages) STMICROELECTRONICS

10 / 238 page

1. The devices with SMPS correspond to commercial code STM32H7B3xIxxQ.

2. For limitations on peripheral features depending on packages, check the available pins/balls in Table 7. STM32H7B3xI pin/ball definition.

3. To maximize the performance, the I/O high-speed at low-voltage feature (HSLV) must be activated when VDD < 2.7 V. This feature is not available on all I/Os (see

Table 90. OCTOSPI characteristics in SDR mode, and Table 91. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus).

4. The I/O high-speed at low-voltage feature (HSLV) at VDD < 2.7 V is not available for OCTOSPIM_P2.

5. The two OCTOSPIs are available only in Muxed mode.

6. A tamper pin can be configured either as passive or active (not both).

7. SPI1, SPI2, SPI3 and SPI6 interfaces give the flexibility to work in an exclusive way in either SPI mode or I2S audio mode.

8. Dedicated I/O supply pad (VDDMMC) or external level shifter are not supported.

9. The ULPI interface is supported. PC2 and PC3 are available on PC2_C and PC3_C, respectively, by closing the internal analog switch (see Table 7. STM32H7B3xI pin/ball

definition).

10. The ULPI interface is not supported.

11. DCMI and PSSI cannot be used simultaneously since they share the same circuitry.

12. For limitations on fast pads or channels depending on packages, check to the available pins/balls in Table 7. STM32H7B3xI pin/ball definition.

13. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2 Power supply supervisor) and connecting PDR_ON pin to VSS. Otherwise the supply

voltage must stay above 1.71 V with the embedded power voltage detector enabled.

14. The junction temperature is limited to 105 °C in VOS0 voltage range.

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