STM32H7B3AI datasheet(20/238 Pages) STMICROELECTRONICS

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3.10

DMA controllers

The devices feature five DMA instances to unload CPU activity:

•

A master direct memory access (MDMA)

The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to

memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface

and a dedicated AHB interface to access Cortex®-M7 TCM memories.

The MDMA is located in the CD domain. It is able to interface with the other DMA controllers located in this

domain to extend the standard DMA capabilities, or can manage peripheral DMA requests directly.

Each of the 16 channels can perform single block transfers, repeated block transfers and linked list transfers.

•

Two dual-port DMAs (DMA1, DMA2) located in the CD domain and connected to the AHB matrix, with FIFO

and request router capabilities.

•

One basic DMA (BDMA1) located in the CD domain and connected to the AHB matrix. This DMA is

dedicated to the DFSDM (see Section 3.26 Digital filter for sigma-delta modulators (DFSDM))

•

One basic DMA (BDMA2) located in the SRD domain, with request router capabilities.

The DMA request router could be considered as an extension of the DMA controller. It routes the DMA peripheral

requests to the DMA controller itself. This allowing managing the DMA requests with a high flexibility, maximizing

the number of DMA requests that run concurrently, as well as generating DMA requests from peripheral output

trigger or DMA event.

3.11

Chrom-ART Accelerator (DMA2D)

The Chrom-Art Accelerator (DMA2D) is a graphical accelerator which offers advanced bit blitting, row data copy

and pixel format conversion. It supports the following functions:

•

Rectangle filling with a fixed color

•

Rectangle copy

•

Rectangle copy with pixel format conversion

•

Rectangle composition with blending and pixel format conversion

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds

dedicated memory to store color lookup tables. The DMA2D also supports block based YCbCr to handle JPEG

decoder output.

An interrupt can be generated when an operation is complete or at a programmed watermark.

All the operations are fully automatized and are running independently from the CPU or the DMAs.

3.12

Chrom-GRC™ (GFXMMU)

The Chrom-GRC™ is a graphical oriented memory management unit aimed at:

•

Optimizing memory usage according to the display shape

•

Manage cache linear accesses to the frame buffer

•

Prefetch data

The display shape is programmable to store only the visible image pixels.

A virtual memory space is provided which is seen by all system masters and can be physically mapped to any

system memory.

An interrupt can be generated in case of buffer overflow or memory transfer error.

3.13

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and handle

up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M7 with FPU core.

•

Closely coupled NVIC gives low-latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Allows early processing of interrupts

•

Processing of late arriving, higher-priority interrupts

•

Support tail chaining

•

Processor context automatically saved

STM32H7B3xI

DMA controllers

DS13139 - Rev 8

page 20/238

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