STM32H7B3AI datasheet(18/238 Pages) STMICROELECTRONICS

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3.7.2

System reset sources

Power-on reset initializes all registers while system reset reinitializes the system except for the debug, part of the

RCC and power controller status registers, as well as the backup power domain.

A system reset is generated in the following cases:

•

Power-on reset (pwr_por_rst)

•

Brownout reset

•

Low level on NRST pin (external reset)

•

Window watchdog

•

Independent watchdog

•

Software reset

•

Low-power mode security reset

•

Exit from Standby

3.8

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up

or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of

the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have

speed selection to better manage internal noise, power consumption and electromagnetic emission.

After reset, all GPIOs are in Analog mode to reduce power consumption.

The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing

to the I/Os registers.

To maximize the performance, the I/O high-speed feature, HSLV, must be activated at low device supply voltage.

This is needed to achieve the performance required for peripherals such as the SDMMC, FMC and OCTOSPI.

The GPIOs are divided into four groups which can be optimized separately (refer to the description of HSLVx bits

of SYSCFG_CCCSR register in RM0455).

The I/O high-speed feature must be used only when VDD is lower than 2.7 V, and both the HSLV user option bits

(VDDIO_HSLV and VDDMMC_HSLV) and HSLVx bits must be set to enable it (refer to RM0455 for details).

STM32H7B3xI

General-purpose input/outputs (GPIOs)

DS13139 - Rev 8

page 18/238

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