STM32H7B3AI datasheet(16/238 Pages) STMICROELECTRONICS

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3.5.3

Voltage regulator

The same voltage regulator supplies the two power domains (CD and SRD). The CD domain can be

independently switched off.

Voltage regulator output can be adjusted according to application needs through six power supply levels:

•

Run mode (VOS0 to VOS3)

–

Scale 0 and scale 1: high performance

–

Scale 2: medium performance and consumption

–

Scale 3: optimized performance and low-power consumption

•

Stop mode (SVOS3 to SVOS5)

–

Scale 3: peripheral with wakeup from stop mode capabilities (UART, SPI, I2C, LPTIM) are operational

–

Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled

The peripheral functionality is disabled but wakeup from Stop mode is possible through GPIO or

asynchronous interrupt.

3.5.4

SMPS step-down converter

The built-in SMPS step-down converter is a highly power-efficient DC/DC non-linear switching regulator that

provides lower power consumption than a conventional voltage regulator (LDO).

The step-down converter can be used to:

•

Directly supply the VCORE domain

–

the SMPS step-down converter operating modes follow the device system operating modes (Run,

Stop, Standby).

–

the SMPS step-down converter output voltage are set according to the selected VOS and SVOS bits

(voltage scaling)

•

Provide intermediate voltage level to supply the internal voltage regulator (LDO)

–

The SMPS step-down converter operating modes follow the device system operating modes (Run,

Stop, Standby).

–

The SMPS step-down converter output equals 1.8 V or 2.5 V according to the selected step-down level

•

Provide an external supply

–

The SMPS step-down converter is forced to external operating mode

–

The SMPS step-down converter output equals 1.8 V or 2.5 V according to the selected step-down level

The 1.8 V or 2.5 V SMPS step-down converter output voltage imposes a minimum VDDSMPS supply of 2.5 V or

3.3 V, respectively. It defines indirectly the minimum VDD supply and I/O level.

3.6

Low-power modes

There are several ways to reduce power consumption on STM32H7B3xI:

•

Decrease dynamic power consumption by slowing down the system clocks even in Run mode and

individually clock gating the peripherals that are not used.

•

Save power consumption when the CPU is idle, by selecting among the available low-power mode

according to the user application needs. This allows achieving the best compromise between short startup

time, low-power consumption, as well as available wakeup sources.

The devices feature several low-power modes:

•

System Run with CSleep (CPU clock stopped)

•

Autonomous with CD domain in DStop (CPU and CPU Domain bus matrix clocks stopped)

•

Autonomous with CD domain in DStop2 (CPU and CPU Domain bus matrix clocks stopped, CPU domain in

retention mode)

•

System Stop (SRD domain clocks stopped) and CD domain in DStop (CPU and CPU Domain bus matrix

clocks stopped)

•

System Stop (SRD domain clocks stopped) and CD domain in DStop2 (CPU and CPU Domain bus matrix

clocks stopped, CPU domain in retention mode)

•

Standby (System, CD and SRD domains powered down)

STM32H7B3xI

Low-power modes

DS13139 - Rev 8

page 16/238

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