STM32H7B3AI datasheet(17/238 Pages) STMICROELECTRONICS

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CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE

(Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex®-M7 core is set after returning from an

interrupt service routine.

The CPU domain can enter low-power mode (DStop or DStop2) when the processor, its subsystem and the

peripherals allocated in the domain enter low-power mode.

If part of the domain is not in low-power mode, the domain remains in the current mode.

Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains

are in DStop or DStop2 mode.

Table 2. System vs domain low-power mode

System power mode

CD domain power mode

SRD domain power mode

Run

DRun/DStop/DStop2

DRun

Stop

DStop/DStop2

DStop

Standby

Some GPIO pins can be used to monitor CPU and domain power states:

Table 3. Overview of low-power mode monitoring pins

Power state monitoring pins

Description

PWR_CSLEEP

CPU clock OFF

PWR_CSTOP

CPU domain in low-power mode

PWR_NDSTOP2

CPU domain retention mode selection

3.7

Reset and clock controller (RCC)

The clock and reset controller is located in the SRD domain. The RCC manages the generation of all the clocks,

as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the

choice of clock sources and allows to apply clock ratios to improve the power consumption. In addition, on some

communication peripherals that are capable to work with two different clock domains (either a bus interface clock

or a kernel peripheral clock), the system frequency can be changed without modifying the baud rate.

3.7.1

Clock management

The devices embed four internal oscillators, two oscillators with external crystal or resonator, two internal

oscillators with fast startup time and three PLLs.

The RCC receives the following clock source inputs:

•

Internal oscillators:

–

64 MHz HSI clock (1% accuracy)

–

48 MHz RC oscillator

–

4 MHz CSI clock

–

32 kHz LSI clock

•

External oscillators:

–

4-50 MHz HSE clock

–

32.768 kHz LSE clock

The RCC provides three PLLs: one for system clock, two for kernel clocks.

The system starts on the HSI clock. The user application can then select the clock configuration.

A high precision can be achieved for the 48 MHz clock by using the embedded clock recovery system (CRS). It

uses the USB SOF signal, the LSE or an external signal (SYNC) to fine tune the oscillator frequency on-the- fly.

STM32H7B3xI

Reset and clock controller (RCC)

DS13139 - Rev 8

page 17/238

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