STM32H7B3AI datasheet(31/238 Pages) STMICROELECTRONICS

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USART modes/features

USART1/2/3/6/10

UART4/5/7/8/9

Continuous communication using DMA

Multiprocessor communication

Synchronous mode (Master/Slave)

Smartcard mode

Single-wire Half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from low power mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

USART data length

7, 8 and 9 bits

Tx/Rx FIFO

Tx/Rx FIFO size

3.39

Low-power universal asynchronous receiver transmitter (LPUART)

The device embeds one Low-power UART (LPUART1). The LPUART supports asynchronous serial

communication with minimum power consumption. It supports half duplex single wire communication and modem

operations (CTS/RTS). It allows multiprocessor communication.

The LPUART embeds a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by

software and is disabled by default.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode.

The wakeup from Stop mode are programmable and can be done on:

•

Start bit detection

•

Any received data frame

•

A specific programmed data frame

•

Specific TXFIFO/RXFIFO status when FIFO mode is enabled.

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even

in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption.

Higher speed clock can be used to reach higher baud rates.

LPUART interface can be served by the DMA controller.

3.40

Serial peripheral interfaces (SPI)/integrated interchip sound interfaces (I2S)

The devices feature up to six SPIs (SPI1/I2S1, SPI2/I2S2, SPI3/I2S3, SPI6/I2S6 and SPI4, SPI5) that allow

communicating up to 125 Mbits/s in master and slave modes, in half-duplex, full-duplex and simplex modes. The

3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 32 bits for SPI1/I2S1,

SPI2/I2S2, SPI3/I2S3, from 4 to 16 bits for the others. All SPI interfaces support SS pulse mode, TI mode,

Hardware CRC calculation, and 16x 8-bit embedded Rx and Tx FIFOs (SPI1/I2S1, SPI2/I2S2, SPI3/I2S3) or 8x

8-bit embedded Rx and Tx FIFOs (SPI4, SPI5, SPI6/I2S6), all with DMA capability. .

Four standard I2S interfaces (multiplexed with SPI1, SPI2, SPI3, SPI6) are available. They can be operated in

master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit

resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported.

When one or all I2S interfaces is/are configured in master mode, the master clock can be output to the external

DAC/codec at 256 times the sampling frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs

with DMA capability.

STM32H7B3xI

Low-power universal asynchronous receiver transmitter (LPUART)

DS13139 - Rev 8

page 31/238

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