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STM32H7B3AI 数据表(PDF) 172 Page - STMicroelectronics |
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STM32H7B3AI 数据表(HTML) 172 Page - STMicroelectronics |
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172 / 238 page ![]() Symbol Parameter Conditions Min(1) Typ(1) Max(1)(2) Unit tsu(SI) Data input setup time ns Slave mode 2 - - th(MI) Data input hold time Master mode 3 - - th(SI) Slave mode 1 - - ta(SO) Data output access time Slave mode 9 13 27 tdis(SO) Data output disable time Slave mode 0 1 5 tv(SO) Data output valid time Slave mode, 2.7 < VDD < 3.6 V - 9/15(3) 11/16(3) Slave mode, 1.62 < VDD < 3.6 V - 9/15(3) 17/27(3) tv(MO) Master mode, 2.7 < VDD < 3.6 V - 1/5(3) 1.5/7(3) Master mode, 1.62 < VDD < 3.6 V - 1/5(3) 2/13(3) th(SO) Data output hold time Slave mode, 1.62 < VDD < 3.6 V 7 - - th(MO) Master mode 0 - - 1. Guaranteed by characterization results. 2. At VOS1, these values are degraded by up to 5 %. 3. Using PC3_C / PC2_C (not available on all packages). Figure 68. SPI timing diagram - slave mode and CPHA = 0 MSv69584V1 SS input CPHA=0 CPOL=0 CPHA=0 CPOL=1 MISO output MOSI input tsu(SI) th(SI) tw(SCKL) tw(SCKH) tc(SCK) tr(SCK) th(SS) tdis(SO) tsu(SS) ta(SO) tv(SO) Next bits IN Last bit OUT First bit IN First bit OUT Next bits OUT th(SO) tf(SCK) Last bit IN STM32H7B3xI Operating conditions DS13139 - Rev 8 page 172/238 |
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