ENC28J60-CSLASHSP datasheet(30/96 Pages) MICROCHIP

30 / 96 page

ENC28J60

DS39662B-page 28

Preliminary

4.2.2

READ BUFFER MEMORY

COMMAND

The Read Buffer Memory (RBM) command allows the

host controller to read bytes from the integrated 8-Kbyte

transmit and receive buffer memory.

If the AUTOINC bit in the ECON2 register is set, the

ERDPT Pointer will automatically increment to point to

the next address after the last bit of each byte is read.

The next address will normally be the current address

incremented by one. However, if the last byte in the

receive buffer is read (ERDPT = ERXND), the ERDPT

Pointer will change to the beginning of the receive

buffer (ERXST). This allows the host controller to read

packets from the receive buffer in a continuous stream

without keeping track of when a wraparound is needed.

If AUTOINC is set when address 1FFFh is read and

ERXND does not point to this address, the Read

Pointer will increment and wrap around to 0000h.

The RBM command is started by pulling the CS pin low.

The RBM opcode is then sent to the ENC28J60,

followed by the 5-bit constant 1Ah. After the RBM com-

mand and constant are sent, the data stored in the

memory pointed to by ERDPT will be shifted out MSb

first on the SO pin. If the host controller continues to

provide clocks on the SCK pin, without raising CS, the

byte pointed to by ERDPT will again be shifted out MSb

first on the SO pin. In this manner, with AUTOINC

enabled, it is possible to continuously read sequential

bytes from the buffer memory without any extra SPI

command overhead. The RBM command is terminated

by raising the CS pin.

4.2.3

WRITE CONTROL REGISTER

COMMAND

The Write Control Register (WCR) command allows

the host controller to write to any of the ETH, MAC and

MII Control registers in any order. The PHY registers

are written to via a special MII register interface (see

Section 3.3.2 “Writing PHY Registers” for more

information).

The WCR command is started by pulling the CS pin

low. The WCR opcode is then sent to the ENC28J60,

followed by a 5-bit address (A4 through A0). The 5-bit

address identifies any of the 32 control registers in the

current bank. After the WCR command and address

are sent, actual data that is to be written is sent, MSb

first. The data will be written to the addressed register

on the rising edge of the SCK line.

The WCR operation is terminated by raising the CS pin.

If the CS line is allowed to go high before eight bits are

loaded, the write will be aborted for that data byte.

Refer to the timing diagram in Figure 4-5 for a more

detailed illustration of the byte write sequence.

FIGURE 4-5:

WRITE CONTROL REGISTER COMMAND SEQUENCE

SCK

23456

1D0

Data Byte

High-Impedance State

Opcode

Address

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