ENC28J60-CSLASHSP datasheet(31/96 Pages) MICROCHIP

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Preliminary

DS39662B-page 29

ENC28J60

4.2.4

WRITE BUFFER MEMORY

COMMAND

The Write Buffer Memory (WBM) command allows the

host controller to write bytes to the integrated 8-Kbyte

transmit and receive buffer memory.

If the AUTOINC bit in the ECON2 register is set, after

the last bit of each byte is written, the EWRPT Pointer

will automatically be incremented to point to the next

sequential address (current address + 1). If address

1FFFh is written with AUTOINC set, the Write Pointer

will increment to 0000h.

The WBM command is started by lowering the CS pin.

The WBM opcode should then be sent to the

ENC28J60, followed by the 5-bit constant 1Ah. After

the WBM command and constant are sent, the data to

be stored in the memory pointed to by EWRPT should

be shifted out MSb first to the ENC28J60. After 8 data

bits are received, the Write Pointer will automatically

increment if AUTOINC is set. The host controller can

continue to provide clocks on the SCK pin and send

data on the SI pin, without raising CS, to keep writing to

the memory. In this manner, with AUTOINC enabled, it

is possible to continuously write sequential bytes to the

buffer memory without any extra SPI command

overhead.

The WBM command is terminated by bringing up the

CS pin. Refer to Figure 4-6 for a detailed illustration of

the write sequence.

4.2.5

BIT FIELD SET COMMAND

The Bit Field Set (BFS) command is used to set up to

8 bits in any of the ETH Control registers. Note that this

command cannot be used on the MAC registers, MII

registers, PHY registers or buffer memory. The BFS com-

mand uses the provided data byte to perform a bit-wise

OR operation on the addressed register contents.

The BFS command is started by pulling the CS pin low.

The BFS opcode is then sent, followed by a 5-bit

address (A4 through A0). The 5-bit address identifies

any of the ETH registers in the current bank. After the

BFS command and address are sent, the data byte

containing the bit field set information should be sent,

MSb first. The supplied data will be logically ORed to

the content of the addressed register on the rising

edge of the SCK line for the D0 bit.

If the CS line is brought high before eight bits are

loaded, the operation will be aborted for that data

byte. The BFS operation is terminated by raising the

CS pin.

4.2.6

BIT FIELD CLEAR COMMAND

The Bit Field Clear (BFC) command is used to clear up

to 8 bits in any of the ETH Control registers. Note that

this command cannot be used on the MAC registers,

MII registers, PHY registers or buffer memory. The BFC

command uses the provided data byte to perform a bit-

wise NOTAND operation on the addressed register

contents. As an example, if a register had the contents

of F1h and the BFC command was executed with an

operand of 17h, then the register would be changed to

have the contents of E0h.

The BFC command is started by lowering the CS pin.

The BFC opcode should then be sent, followed by a

5-bit address (A4 through A0). The 5-bit address

identifies any of the ETH registers in the current bank.

After the BFC command and address are sent, a data

byte containing the bit field clear information should

be sent, MSb first. The supplied data will be logically

inverted and subsequently ANDed to the contents of

the addressed register on the rising edge of the SCK

line for the D0 bit.

The BFC operation is terminated by bringing the CS

pin high. If CS is brought high before eight bits are

loaded, the operation will be aborted for that data

byte.

FIGURE 4-6:

WRITE BUFFER MEMORY COMMAND SEQUENCE

SCK

23456789

10 11 12

13 14 15 16 17 18 19

20 21 22

1D0

7654321

Data Byte 0

Data Byte 1

Opcode

Address

High-Impedance State

ENC28J60-C/SP 数据表(PDF) 31 Page - Microchip Technology

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