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ENC28J60-C/SP 数据表(PDF) 16 Page - Microchip Technology |
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ENC28J60-C/SP 数据表(HTML) 16 Page - Microchip Technology |
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16 / 96 page  ENC28J60 DS39662B-page 14 Preliminary © 2006 Microchip Technology Inc. EPMCSL Pattern Match Checksum Low Byte (EPMCS<7:0>) 0000 0000 51 EPMCSH Pattern Match Checksum High Byte (EPMCS<15:0>) 0000 0000 51 EPMOL Pattern Match Offset Low Byte (EPMO<7:0>) 0000 0000 51 EPMOH — — — Pattern Match Offset High Byte (EPMO<12:8>) ---0 0000 51 ERXFCON UCEN ANDOR CRCEN PMEN MPEN HTEN MCEN BCEN 1010 0001 48 EPKTCNT Ethernet Packet Count 0000 0000 43 MACON1 — — — r TXPAUS RXPAUS PASSALL MARXEN ---0 0000 34 MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX 0000 0000 35 MACON4 — DEFER BPEN NOBKOFF — —r r -000 --00 36 MABBIPG — Back-to-Back Inter-Packet Gap (BBIPG<6:0>) -000 0000 36 MAIPGL — Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) -000 0000 34 MAIPGH — Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) -000 0000 34 MACLCON1 — — — — Retransmission Maximum (RETMAX<3:0>) ---- 1111 34 MACLCON2 — — Collision Window (COLWIN<5:0>) --11 0111 34 MAMXFLL Maximum Frame Length Low Byte (MAMXFL<7:0>) 0000 0000 34 MAMXFLH Maximum Frame Length High Byte (MAMXFL<15:8>) 0000 0110 34 MICMD — — — — — — MIISCAN MIIRD ---- --00 21 MIREGADR — — — MII Register Address (MIREGADR<4:0>) ---0 0000 19 MIWRL MII Write Data Low Byte (MIWR<7:0>) 0000 0000 19 MIWRH MII Write Data High Byte (MIWR<15:8>) 0000 0000 19 MIRDL MII Read Data Low Byte (MIRD<7:0>) 0000 0000 19 MIRDH MII Read Data High Byte(MIRD<15:8>) 0000 0000 19 MAADR5 MAC Address Byte 5 (MAADR<15:8>) 0000 0000 34 MAADR6 MAC Address Byte 6 (MAADR<7:0>) 0000 0000 34 MAADR3 MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 0000 0000 34 MAADR4 MAC Address Byte 4 (MAADR<23:16>) 0000 0000 34 MAADR1 MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 0000 0000 34 MAADR2 MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2 0000 0000 34 EBSTSD Built-in Self-Test Fill Seed (EBSTSD<7:0>) 0000 0000 76 EBSTCON PSV2 PSV1 PSV0 PSEL TMSEL1 TMSEL0 TME BISTST 0000 0000 75 EBSTCSL Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) 0000 0000 76 EBSTCSH Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) 0000 0000 76 MISTAT — — — — r NVALID SCAN BUSY ---- 0000 21 EREVID(2) — — — Ethernet Revision ID (EREVID<4:0>) ---q qqqq 22 ECOCON(3) — — — — — COCON2 COCON1 COCON0 ---- -100 6 EFLOCON — — — — — FULDPXS FCEN1 FCEN0 ---- -000 56 EPAUSL Pause Timer Value Low Byte (EPAUS<7:0>) 0000 0000 57 EPAUSH Pause Timer Value High Byte (EPAUS<15:8>) 0001 0000 57 TABLE 3-2: ENC28J60 CONTROL REGISTER SUMMARY (CONTINUED) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Reset Details on Page Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition, r = reserved, do not modify. Note 1: CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets. 2: EREVID is a read-only register. 3: ECOCON resets to ‘---- -100’ on Power-on Reset and ‘---- -uuu’ on all other Resets. |
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