ENC28J60-CSLASHSP datasheet(65/96 Pages) MICROCHIP

65 / 96 page

Preliminary

DS39662B-page 63

ENC28J60

12.0

INTERRUPTS

The ENC28J60 has multiple interrupt sources and an

interrupt output pin to signal the occurrence of events

to the host controller. The interrupt pin is designed for

use by a host controller that is capable of detecting fall-

ing edges.

Interrupts are managed with two registers. The EIE

each interrupt source, while the EIR register contains

the corresponding interrupt flag bits. When an interrupt

occurs, the interrupt flag is set. If the interrupt is

enabled in the EIE register and the INTIE global inter-

rupt enable bit is set, the INT pin will be driven low (see

Figure 12-1).

When an enabled interrupt occurs, the interrupt pin will

remain low until all flags which are causing the interrupt

are cleared or masked off (enable bit is cleared) by the

host controller. If more than one interrupt source is

enabled, the host controller must poll each flag in the

EIR register to determine the source(s) of the interrupt.

It is recommended that the Bit Field Clear (BFC) SPI

command be used to reset the flag bits in the EIR reg-

ister rather than the normal Write Control Register

(WCR) command. This is necessary to prevent unin-

tentionally altering a flag that changes during the write

command. The BFC and WCR commands are dis-

cussed in detail in Section 4.0 “Serial Peripheral

Interface (SPI)”.

After an interrupt occurs, the host controller should

clear the global enable bit for the interrupt pin before

servicing the interrupt. Clearing the enable bit will

cause the interrupt pin to return to the non-asserted

state (high). Doing so will prevent the host controller

from missing a falling edge should another interrupt

occur while the immediate interrupt is being serviced.

After the interrupt has been serviced, the global enable

bit may be restored. If an interrupt event occurred while

the previous interrupt was being processed, the act of

resetting the global enable bit will cause a new falling

edge on the interrupt pin to occur.

FIGURE 12-1:

ENC28J60 INTERRUPT LOGIC

Note:

Except for the LINKIF interrupt flag,

interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the associ-

ated global enable bit. User software

should ensure the appropriate interrupt flag

bits are clear prior to enabling an interrupt.

This feature allows for software polling.

PKTIF

PKTIE

DMAIF

DMAIE

LINKIE

TXIF

TXIE

INT

INTIE

TXERIF

TXERIE

RXERIF

RXERIE

LINKIF

PGIF

PGEIE

PLNKIF

PLNKIE

INT

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