ENC28J60-CSLASHSP datasheet(18/96 Pages) MICROCHIP

18 / 96 page

ENC28J60

DS39662B-page 16

Preliminary

3.1.2

ECON2 REGISTER

The ECON2 register, shown in Register 3-2, is used to

control other main functions of the ENC28J60.

ECON2: ETHERNET CONTROL REGISTER 2

R/W-1

R/W-0(1)

R/W-0

U-0

AUTOINC

PKTDEC

PWRSV

VRPS

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

AUTOINC: Automatic Buffer Pointer Increment Enable bit

= Automatically increment ERDPT or EWRPT on reading from or writing to EDATA

= Do not automatically change ERDPT and EWRPT after the buffer is accessed

bit 6

PKTDEC: Packet Decrement bit

= Decrement the EPKTCNT register by one

= Leave EPKTCNT unchanged

bit 5

PWRSV: Power Save Enable bit

= MAC, PHY and control logic are in Low-Power Sleep mode

= Normal operation

bit 4

Reserved: Maintain as ‘0’

bit 3

VRPS: Voltage Regulator Power Save Enable bit

When PWRSV = 1:

= Internal voltage regulator is in Low-Current mode

= Internal voltage regulator is in Normal Current mode

When PWRSV = 0:

The bit is ignored; the regulator always outputs as much current as the device requires.

bit 2-0

Unimplemented: Read as ‘0’

Note 1:

This bit is automatically cleared once it is set.

ENC28J60-C/SP 数据表(PDF) 18 Page - Microchip Technology

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