ENC28J60-CSLASHSP datasheet(36/96 Pages) MICROCHIP

36 / 96 page

ENC28J60

DS39662B-page 34

Preliminary

6.5

MAC Initialization Settings

Several of the MAC registers require configuration

during initialization. This only needs to be done once;

the order of programming is unimportant.

Set the MARXEN bit in MACON1 to enable the

MAC to receive frames. If using full duplex, most

applications should also set TXPAUS and

RXPAUS to allow IEEE defined flow control to

function.

Configure

the

PADCFG,

TXCRCEN

and

FULDPX bits of MACON3. Most applications

should enable automatic padding to at least

60 bytes and always append a valid CRC. For

convenience, many applications may wish to set

the FRMLNEN bit as well to enable frame length

status reporting. The FULDPX bit should be set

if the application will be connected to a

full-duplex configured remote node; otherwise, it

should be left clear.

Configure the bits in MACON4. For conform-

ance to the IEEE 802.3 standard, set the

DEFER bit.

Program the MAMXFL registers with the maxi-

mum frame length to be permitted to be received

or transmitted. Normal network nodes are

designed to handle packets that are 1518 bytes

or less.

Configure the Back-to-Back Inter-Packet Gap

gram this register with 15h when Full-Duplex

mode is used and 12h when Half-Duplex mode

is used.

Configure the Non-Back-to-Back Inter-Packet

Gap register low byte, MAIPGL. Most applications

will program this register with 12h.

If half duplex is used, the Non-Back-to-Back

Inter-Packet Gap register high byte, MAIPGH,

should be programmed. Most applications will

program this register to 0Ch.

If Half-Duplex mode is used, program the

Retransmission and Collision Window registers,

MACLCON1 and MACLCON2. Most applications

will not need to change the default Reset values.

If the network is spread over exceptionally long

cables, the default value of MACLCON2 may

need to be increased.

Program the local MAC address into the

MAADR1:MAADR6 registers.

MACON1: MAC CONTROL REGISTER 1

U-0

R-0

R/W-0

—

TXPAUS

RXPAUS

PASSALL

MARXEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

Unimplemented: Read as ‘0’

bit 4

Reserved: Maintain as ‘0’

bit 3

TXPAUS: Pause Control Frame Transmission Enable bit

= Allow the MAC to transmit pause control frames (needed for flow control in full duplex)

= Disallow pause frame transmissions

bit 2

RXPAUS: Pause Control Frame Reception Enable bit

= Inhibit transmissions when pause control frames are received (normal operation)

= Ignore pause control frames which are received

bit 1

PASSALL: Pass All Received Frames Enable bit

= Control frames received by the MAC will be written into the receive buffer if not filtered out

= Control frames will be discarded after being processed by the MAC (normal operation)

bit 0

MARXEN: MAC Receive Enable bit

= Enable packets to be received by the MAC

= Disable packet reception

ENC28J60-C/SP 数据表(PDF) 36 Page - Microchip Technology

ENC28J60-C/SP 数据表(HTML) 36 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表下载