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ENC28J60-C/SP 数据表(PDF) 38 Page - Microchip Technology |
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ENC28J60-C/SP 数据表(HTML) 38 Page - Microchip Technology |
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38 / 96 page  ENC28J60 DS39662B-page 36 Preliminary © 2006 Microchip Technology Inc. REGISTER 6-3: MACON4: MAC CONTROL REGISTER 4 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-0 R-0 — DEFER BPEN NOBKOFF — —r r bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 DEFER: Defer Transmission Enable bit (applies to half duplex only) 1 = When the medium is occupied, the MAC will wait indefinitely for it to become free when attempting to transmit (use this setting for 802.3 compliance) 0 = When the medium is occupied, the MAC will abort the transmission after the excessive deferral limit is reached bit 5 BPEN: No Backoff During Backpressure Enable bit (applies to half duplex only) 1 = After incidentally causing a collision during backpressure, the MAC will immediately begin retransmitting 0 = After incidentally causing a collision during backpressure, the MAC will delay using the Binary Exponential Backoff algorithm before attempting to retransmit (normal operation) bit 4 NOBKOFF: No Backoff Enable bit (applies to half duplex only) 1 = After any collision, the MAC will immediately begin retransmitting 0 = After any collision, the MAC will delay using the Binary Exponential Backoff algorithm before attempting to retransmit (normal operation) bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 Reserved: Maintain as ‘0’ REGISTER 6-4: MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-0 BBIPG6:BBIPG0: Back-to-Back Inter-Packet Gap Delay Time bits When FULDPX (MACON3<0>) = 1: Nibble time offset delay between the end of one transmission and the beginning of the next in a back-to-back sequence. The register value should be programmed to the desired period in nibble times minus 3. The recommended setting is 15h which represents the minimum IEEE specified Inter-Packet Gap (IPG) of 9.6 μs. When FULDPX (MACON3<0>) = 0: Nibble time offset delay between the end of one transmission and the beginning of the next in a back-to-back sequence. The register value should be programmed to the desired period in nibble times minus 6. The recommended setting is 12h which represents the minimum IEEE specified Inter-Packet Gap (IPG) of 9.6 μs. |
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