ENC28J60-CSLASHSP datasheet(74/96 Pages) MICROCHIP

74 / 96 page

ENC28J60

DS39662B-page 72

Preliminary

13.2

Checksum Calculations

The checksum calculation logic treats the source data as

a series of 16-bit big-endian integers. If the source range

contains an odd number of bytes, a padding byte of 00h

is effectively added to the end of the series for purposes

of calculating the checksum. The calculated checksum

is the 16-bit one’s complement of the one’s complement

sum of all 16-bit integers. For example, if the bytes

included in the checksum were {89h, ABh, CDh}, the

checksum would begin by computing 89ABh + CD00h.

A carry out of the 16th bit would occur in the example, so

in 16-bit one’s complement arithmetic, it would be added

back to the first bit. The resulting value of 56ACh would

finally be complemented to achieve a checksum of

A953h.

To calculate a checksum:

Program the EDMAST and EDMAND register

pairs to point to the first and last bytes of buffer

data to be included in the checksum. Care should

be taken when programming these Pointers to

prevent a never ending checksum calculation

due to receive buffer wrapping.

To generate an optional interrupt when the

checksum calculation is done, clear EIR.DMAIF,

set EIE.DMAIE and set EIE.INTIE.

Start the calculation by setting ECON1.CSUMEN

and ECON1.DMAST.

When the checksum is finished being calculated, the

hardware will clear the DMAST bit, set the DMAIF bit

and an interrupt will be generated if enabled. The DMA

Pointers will not be modified and no memory will be

written to. The EDMACSH and EDMACSL registers will

contain the calculated checksum. The host controller

may write this value into a packet, compare this value

with a received checksum, or use it for other purposes.

Various protocols, such as TCP and IP, have a checksum

field inside a range of data which the checksum covers.

If such a packet is received and the host controller needs

to validate the checksum, it can do the following:

Read the checksum from the packet and save it

to a temporary location

Write zeros to the checksum field.

Calculate a new checksum using the DMA

controller.

Compare the results with the saved checksum

from step 1.

Writing to the receive buffer is permitted when the write

address is protected by means of the ERXRDPT

Pointers. See Section 7.2 “Receiving Packets” for

additional information.

The IP checksum has unique mathematical properties

which may be used in some cases to reduce the

processing requirements further. Writing to the receive

buffer may be unnecessary in some applications.

When operating the DMA in Checksum mode, it will

take one main clock cycle for every byte included in the

checksum. As a result, if a checksum over 1446 bytes

were performed, the DMA module would require

slightly more than 57.84

μs to complete the operation.

TABLE 13-1:

SUMMARY OF REGISTERS ASSOCIATED WITH THE DMA CONTROLLER

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

EIE

INTIE

PKTIE

DMAIE

LINKIE

TXIE

TXERIE

RXERIE

EIR

—

PKTIF

DMAIF

LINKIF

TXIF

TXERIF

RXERIF

ECON1

TXRST

RXRST

DMAST

CSUMEN

TXRTS

RXEN

BSEL1

BSEL0

ERXNDL

RX End Low Byte (ERXND<7:0>)

ERXNDH

—

RX End High Byte (ERXND<12:8>)

EDMASTL

DMA Start Low Byte (EDMAST<7:0>)

EDMASTH

—

DMA Start High Byte (EDMAST<12:8>)

EDMANDL

DMA End Low Byte (EDMAND<7:0>)

EDMANDH

—

DMA End High Byte (EDMAND<12:8>)

EDMADSTL DMA Destination Low Byte (EDMADST<7:0>)

EDMADSTH

—

DMA Destination High Byte (EDMADST<12:8>)

EDMACSL

DMA Checksum Low Byte (EDMACS<7:0>)

EDMACSH

DMA Checksum High Byte (EDMACS<15:8>)

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the DMA controller.

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