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ENC28J60-C/SP 数据表(PDF) 14 Page - Microchip Technology |
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ENC28J60-C/SP 数据表(HTML) 14 Page - Microchip Technology |
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14 / 96 page  ENC28J60 DS39662B-page 12 Preliminary © 2006 Microchip Technology Inc. 3.1 Control Registers The Control Registers provide the main interface between the host controller and the on-chip Ethernet controller logic. Writing to these registers controls the operation of the interface, while reading the registers allows the host controller to monitor operations. The Control Register memory is partitioned into four banks, selectable by the bank select bits BSEL1:BSEL0 in the ECON1 register. Each bank is 32 bytes long and addressed by a 5-bit address value. The last five locations (1Bh to 1Fh) of all banks point to a common set of registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers used in controlling and monitoring the operation of the device. Their common mapping allows easy access without switching the bank. The ECON1 and ECON2 registers are discussed later in this section. Some of the available addresses are unimplemented. Any attempts to write to these locations are ignored while reads return ‘0’s. The register at address 1Ah in each bank is reserved; read and write operations should not be performed on this register. All other reserved registers may be read, but their contents must not be changed. When reading and writing to registers which contain reserved bits, any rules stated in the register definition should be observed. Control registers for the ENC28J60 are generically grouped as ETH, MAC and MII registers. Register names starting with “E” belong to the ETH group. Similarly, registers names starting with “MA” belong to the MAC group and registers prefixed with “MI” belong to the MII group. TABLE 3-1: ENC28J60 CONTROL REGISTER MAP Bank 0 Bank 1 Bank 2 Bank 3 Address Name Address Name Address Name Address Name 00h ERDPTL 00h EHT0 00h MACON1 00h MAADR5 01h ERDPTH 01h EHT1 01h Reserved 01h MAADR6 02h EWRPTL 02h EHT2 02h MACON3 02h MAADR3 03h EWRPTH 03h EHT3 03h MACON4 03h MAADR4 04h ETXSTL 04h EHT4 04h MABBIPG 04h MAADR1 05h ETXSTH 05h EHT5 05h — 05h MAADR2 06h ETXNDL 06h EHT6 06h MAIPGL 06h EBSTSD 07h ETXNDH 07h EHT7 07h MAIPGH 07h EBSTCON 08h ERXSTL 08h EPMM0 08h MACLCON1 08h EBSTCSL 09h ERXSTH 09h EPMM1 09h MACLCON2 09h EBSTCSH 0Ah ERXNDL 0Ah EPMM2 0Ah MAMXFLL 0Ah MISTAT 0Bh ERXNDH 0Bh EPMM3 0Bh MAMXFLH 0Bh — 0Ch ERXRDPTL 0Ch EPMM4 0Ch Reserved 0Ch — 0Dh ERXRDPTH 0Dh EPMM5 0Dh Reserved 0Dh — 0Eh ERXWRPTL 0Eh EPMM6 0Eh Reserved 0Eh — 0Fh ERXWRPTH 0Fh EPMM7 0Fh —0Fh — 10h EDMASTL 10h EPMCSL 10h Reserved 10h — 11h EDMASTH 11h EPMCSH 11h Reserved 11h — 12h EDMANDL 12h — 12h MICMD 12h EREVID 13h EDMANDH 13h — 13h — 13h — 14h EDMADSTL 14h EPMOL 14h MIREGADR 14h — 15h EDMADSTH 15h EPMOH 15h Reserved 15h ECOCON 16h EDMACSL 16h Reserved 16h MIWRL 16h Reserved 17h EDMACSH 17h Reserved 17h MIWRH 17h EFLOCON 18h — 18h ERXFCON 18h MIRDL 18h EPAUSL 19h — 19h EPKTCNT 19h MIRDH 19h EPAUSH 1Ah Reserved 1Ah Reserved 1Ah Reserved 1Ah Reserved 1Bh EIE 1Bh EIE 1Bh EIE 1Bh EIE 1Ch EIR 1Ch EIR 1Ch EIR 1Ch EIR 1Dh ESTAT 1Dh ESTAT 1Dh ESTAT 1Dh ESTAT 1Eh ECON2 1Eh ECON2 1Eh ECON2 1Eh ECON2 1Fh ECON1 1Fh ECON1 1Fh ECON1 1Fh ECON1 |
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